| An ultra-low power, reconfigurable, aging resilient RO PUF for IoT applications S Khan, AP Shah, N Gupta, SS Chouhan, JG Pandey, SK Vishvakarma Microelectronics journal 92, 104605, 2019 | 30 | 2019 |
| Utilizing manufacturing variations to design a tri-state flip-flop PUF for IoT security applications S Khan, AP Shah, SS Chouhan, S Rani, N Gupta, JG Pandey, ... Analog Integrated Circuits and Signal Processing 103 (3), 477-492, 2020 | 23 | 2020 |
| A symmetric D flip-flop based PUF with improved uniqueness S Khan, AP Shah, SS Chouhan, N Gupta, JG Pandey, SK Vishvakarma Microelectronics Reliability 106, 113595, 2020 | 19 | 2020 |
| An energy‐efficient data‐dependent low‐power 10T SRAM cell design for LiFi enabled smart street lighting system application N Gupta, V Sharma, AP Shah, S Khan, M Huebner, SK Vishvakarma International Journal of Numerical Modelling: Electronic Networks, Devices …, 2020 | 13 | 2020 |
| Efficient low-precision cordic algorithm for hardware implementation of artificial neural network G Raut, V Bhartiy, G Rajput, S Khan, A Beohar, SK Vishvakarma VLSI Design and Test: 23rd International Symposium, VDAT 2019, Indore, India …, 2019 | 10 | 2019 |
| On-chip adaptive vdd scaled architecture of reliable SRAM cell with improved soft error tolerance N Gupta, AP Shah, RS Kumar, T Gupta, S Khan, SK Vishvakarma IEEE Transactions on Device and Materials Reliability 20 (4), 694-705, 2020 | 9 | 2020 |
| Error-tolerant reconfigurable VDD 10T SRAM architecture for IoT applications N Gupta, AP Shah, S Khan, SK Vishvakarma, M Waltl, P Girard Electronics 10 (14), 1718, 2021 | 6 | 2021 |
| ASIC Implementation Of Biologically Inspired Spiking Neural Network G Rajput, G Raut, S Khan, N Gupta, A Behor, SK Vishvakarma 2019 9th International Conference on Emerging Trends in Engineering and …, 2019 | 2 | 2019 |
| An ultra low power AES architecture for IoT S Khan, N Gupta, G Raut, G Rajput, JG Pandey, SK Vishvakarma International Symposium on VLSI Design and Test, 334-344, 2019 | 2 | 2019 |
| A VLSI architecture for the PRESENT block cipher with FPGA and ASIC implementations JG Pandey, T Goel, M Nayak, C Mitharwal, S Khan, SK Vishvakarma, ... VLSI Design and Test: 22nd International Symposium, VDAT 2018, Madurai …, 2019 | 2 | 2019 |
| Low leakage highly stable robust ultra low power 8T SRAM cell N Gupta, T Gupta, S Khan, A Vishwakarma, SK Vishvakarma VLSI Design and Test: 23rd International Symposium, VDAT 2019, Indore, India …, 2019 | 2 | 2019 |
| Pass transistor XOR gate based radiation hardened RO-PUF SF Naz, S Khan, AP Shah International Symposium on VLSI Design and Test, 331-344, 2022 | 1 | 2022 |
| D flip-flop based TRNG with zero hardware cost for IoT security applications S Khan, AP Shah, SS Chouhan, JG Pandey, SK Vishvakarma Microelectronics Reliability 120, 114098, 2021 | 1 | 2021 |
| Dual-edge triggered lightweight implementation of AES for IoT security S Khan, N Gupta, A Vishvakarma, SS Chouhan, JG Pandey, ... VLSI Design and Test: 23rd International Symposium, VDAT 2019, Indore, India …, 2019 | 1 | 2019 |
| Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications. Electronics 2021, 10, 1718 N Gupta, AP Shah, S Khan, SK Vishvakarma, M Waltl, P Girard s Note: MDPI stays neutral with regard to jurisdictional claims in published …, 2021 | | 2021 |
Dr. Santosh Kumar VishvakarmaIndian Institute of Technology IndoreEmail yang diverifikasi di iiti.ac.in