| TrueNorth: Accelerating from zero to 64 million neurons in 10 years MV DeBole, B Taba, A Amir, F Akopyan, A Andreopoulos, WP Risk, ... Computer 52 (5), 20-29, 2019 | 262 | 2019 |
| Automated layout for integrated circuits with nonstandard cells R Manohar, R Karmazin, CTO Otero US Patent 9,852,253, 2017 | 85 | 2017 |
| Neural inference at the frontier of energy, space, and time DS Modha, F Akopyan, A Andreopoulos, R Appuswamy, JV Arthur, ... Science 382 (6668), 329-335, 2023 | 67 | 2023 |
| Static power reduction techniques for asynchronous circuits C Ortega, J Tse, R Manohar 2010 IEEE Symposium on Asynchronous Circuits and Systems, 52-61, 2010 | 49 | 2010 |
| A split-foundry asynchronous FPGA B Hill, R Karmazin, CTO Otero, J Tse, R Manohar Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 1-4, 2013 | 47 | 2013 |
| celltk: Automated layout for asynchronous circuits with nonstandard cells R Karmazin, CTO Otero, R Manohar 2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems …, 2013 | 39 | 2013 |
| Automatic obfuscated cell layout for trusted split-foundry design CTO Otero, J Tse, R Karmazin, B Hill, R Manohar 2015 IEEE International Symposium on Hardware Oriented Security and Trust …, 2015 | 32 | 2015 |
| Variability in 3-D integrated circuits F Akopyan, CTO Otero, D Fang, SJ Jackson, R Manohar 2008 IEEE Custom Integrated Circuits Conference, 659-662, 2008 | 27 | 2008 |
| AES hardware-software co-design in WSN CTO Otero, J Tse, R Manohar 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems …, 2015 | 18 | 2015 |
| ULSNAP: An ultra-low power event-driven microcontroller for sensor network nodes CTO Otero, J Tse, R Karmazin, B Hill, R Manohar Fifteenth International Symposium on Quality Electronic Design, 667-674, 2014 | 18 | 2014 |
| A transient electrothermal analysis of three-dimensional integrated circuits TR Harris, S Priyadarshi, S Melamed, C Ortega, R Manohar, SR Dooley, ... IEEE Transactions on Components, Packaging and Manufacturing Technology 2 (4 …, 2012 | 17 | 2012 |
| Timing driven placement for quasi delay-insensitive circuits R Karmazin, S Longfield, CTO Otero, R Manohar 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems …, 2015 | 14 | 2015 |
| Dynamic electrothermal simulation of three-dimensional integrated circuits using standard cell macromodels S Priyadarshi, TR Harris, S Melamed, C Otero, NM Kriplani, ... IET circuits, devices & systems 6 (1), 35-44, 2012 | 12 | 2012 |
| IBM NorthPole neural inference machine DS Modha, F Akopyan, A Andreopoulos, R Appuswamy, JV Arthur, ... 2023 IEEE Hot Chips 35 Symposium (HCS), 1-58, 2023 | 8 | 2023 |
| Hybrid Synchronous-Asynchronous Tool Flow for Emerging VLSI Design F Akopyan, CTO Otero, R Manohar International Workshop on Logic & Synthesis, 2016 | 7 | 2016 |
| 11.4 ibm northpole: An architecture for neural network inference with a 12nm chip AS Cassidy, JV Arthur, F Akopyan, A Andreopoulos, R Appuswamy, ... 2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 214-215, 2024 | 5 | 2024 |
| 3d neural inference processing unit architectures AS Cassidy, FA Akopyan, R Appuswamy, JV Arthur, P Datta, MV DeBole, ... US Patent App. 16/662,532, 2021 | 2 | 2021 |
| Maximization of profits in import activities through a hybrid algorithm based on fictional games with multiple suppliers AM Daza, C Otero, C Paternina The Second European International Conference on Industrial Engineering and …, 2018 | 2 | 2018 |
| Neural network weight distribution from a grid of memory elements J Sawada, DS Modha, AS Cassidy, JV Arthur, TK Nayak, CO Otero, ... US Patent 11,521,085, 2022 | 1 | 2022 |
| Modular neural network computing apparatus with distributed neural network storage J Sawada, DS Modha, JV Arthur, AS Cassidy, P Datta, R Appuswamy, ... US Patent App. 17/077,720, 2022 | 1 | 2022 |
Rajit ManoharYale UniversityEmail yang diverifikasi di yale.edu