A 460 mhz at 397 mv, 2.6 ghz at 1.3 v, 32 bits vliw dsp embedding f max tracking E Beigne, A Valentian, I Miro-Panades, R Wilson, P Flatresse, F Abouzeid, ...
IEEE Journal of Solid-State Circuits 50 (1), 125-136, 2014
58 2014 8.4 a 0.33 v/-40 c process/temperature closed-loop compensation soc embedding all-digital clock multiplier and dc-dc converter exploiting fdsoi 28nm back-gate biasing S Clerc, M Saligane, F Abouzeid, M Cochet, JM Daveau, C Bottoni, D Bol, ...
2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015
54 2015 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking R Wilson, E Beigne, P Flatresse, A Valentian, F Abouzeid, T Benoist, ...
2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014
52 2014 193 MOPS/mW@ 162 MOPS, 0.32 V to 1.15 V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing D Rossi, A Pullini, I Loi, M Gautschi, FK Gurkaynak, A Teman, ...
2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX), 1-3, 2016
45 2016 A 225 μm M Cochet, B Keller, S Clerc, F Abouzeid, A Cathelin, JL Autran, P Roche, ...
IEEE Solid-State Circuits Letters 1 (1), 14-17, 2018
43 2018 The Fourth Terminal: Benefits of Body-Biasing Techniques for FDSOI Circuits and Systems S Clerc, T Di Gilio, A Cathelin
Springer, 2020
41 2020 Scalable 0.35 V to 1.2 V SRAM bitcell design from 65 nm CMOS to 28 nm FDSOI F Abouzeid, A Bienfait, KC Akyel, A Feki, S Clerc, L Ciampolini, F Giner, ...
IEEE Journal of Solid-State Circuits 49 (7), 1499-1505, 2014
39 2014 A 2.7 pJ/cycle 16 MHz, 0.7 G Lallement, F Abouzeid, M Cochet, JM Daveau, P Roche, JL Autran
IEEE Journal of Solid-State Circuits 53 (7), 2088-2100, 2018
37 2018 Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs E Beigné, A Valentian, B Giraud, O Thomas, T Benoist, Y Thonnart, ...
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 613-618, 2013
36 2013 Heavy ions test result on a 65nm sparc-v8 radiation-hard microprocessor C Bottoni, M Glorieux, JM Daveau, G Gasiot, F Abouzeid, S Clerc, ...
2014 IEEE International Reliability Physics Symposium, 5F. 5.1-5F. 5.6, 2014
27 2014 28nm CMOS, energy efficient and variability tolerant, 350mV-to-1.0 V, 10MHz/700MHz, 252bits frame error-decoder F Abouzeid, S Clerc, B Pelloux-Prayer, F Argoud, P Roche
2012 Proceedings of the ESSCIRC (ESSCIRC), 153-156, 2012
24 2012 A 45nm CMOS 0.35 V-optimized standard cell library for ultra-low power applications F Abouzeid, S Clerc, F Firmin, M Renaudin, G Sicard
Proceedings of the 2009 ACM/IEEE international symposium on Low power …, 2009
23 2009 A 65nm SRAM achieving 250mV retention and 350mV, 1MHz, 55fJ/bit access energy, with bit-interleaved radiation soft error tolerance S Clerc, F Abouzeid, G Gasiot, D Gauthier, P Roche
2012 Proceedings of the ESSCIRC (ESSCIRC), 313-316, 2012
19 2012 Sub-threshold 10T SRAM bit cell with read/write XY selection A Feki, B Allard, D Turgis, JC Lafont, FT Drissi, F Abouzeid, S Haendler
Solid-State Electronics 106, 1-11, 2015
18 2015 Space radiation and reliability qualifications on 65nm CMOS 600MHz microprocessors S Clerc, F Abouzeid, G Gasiot, JM Daveau, C Bottoni, M Glorieux, ...
2013 IEEE International Reliability Physics Symposium (IRPS), 6C. 1.1-6C. 1.7, 2013
18 2013 Experimental soft error rate of several flip-flop designs representative of production chip in 32 nm CMOS technology G Gasiot, M Glorieux, S Clerc, D Soussan, F Abouzeid, P Roche
IEEE Transactions on Nuclear Science 60 (6), 4226-4231, 2013
17 2013 Q-learning-based adaptive power management for IoT system-on-chips with embedded power states Y Debizet, G Lallement, F Abouzeid, P Roche, JL Autran
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018
15 2018 Process variability effect on soft error rate by characterization of large number of samples G Gasiot, A Castelnovo, M Glorieux, F Abouzeid, S Clerc, P Roche
IEEE Transactions on Nuclear Science 59 (6), 2914-2919, 2012
15 2012 A 1.1-pJ/cycle, 20-MHz, 0.42-V temperature compensated ARM Cortex-M0+ SoC with adaptive self body-biasing in FD-SOI G Lallement, F Abouzeid, JM Daveau, P Roche, JL Autran
IEEE Solid-State Circuits Letters 1 (7), 174-177, 2019
14 2019 28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors F Abouzeid, S Clerc, C Bottoni, B Coeffic, JM Daveau, D Croain, G Gasiot, ...
ESSCIRC Conference 2015-41st European Solid-State Circuits Conference …, 2015
14 2015 
Philippe RocheFellowEmail yang diverifikasi di st.com