RAMP: Resource-aware mapping for CGRAs S Dave, M Balasubramanian, A Shrivastava
2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), 1-6, 2018
94 2018 CRIMSON: Compute-intensive loop acceleration by randomized iterative modulo scheduling and optimized mapping on CGRAs M Balasubramanian, A Shrivastava
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020
25 2020 LASER: A hardware/software approach to accelerate complicated loops on CGRAs M Balasubramanian, S Dave, A Shrivastava, R Jeyapaul
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018
25 2018 Pathseeker: a fast mapping algorithm for cgras M Balasubramanian, A Shrivastava
2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 268-273, 2022
19 2022 Ureca: Unified register file for cgras S Dave, M Balasubramanian, A Shrivastava
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018
12 2018 Ramp: Resource-aware mapping for cgras. In 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC) S Dave, M Balasubramanian, A Shrivastava
IEEE, 2018
11 2018 Hybrid and efficient approach to accelerate complicated loops on coarse-grained reconfigurable arrays (cgra) accelerators M Balasubramanian, S Dave, A Shrivastava, R Jeyapaul
US Patent App. 16/172,254, 2020
8 2020 Sparse, low-bias, and scalable estimation of high dimensional vector autoregressive models via union of intersections T Ruiz, M Balasubramanian, KE Bouchard, S Bhattacharyya
arXiv preprint arXiv:1908.11464, 2019
5 2019 Optimizing the Union of Intersections LASSO ( M Balasubramanian, T Ruiz, B Cook, S Bhattacharyya, A Shrivastava, ...
arXiv preprint arXiv:1808.06992, 2018
4 2018 PathSeeker: A Fast Mapping Algorithm for CGRAs. In 2022 Design, Automation Test in Europe Conference Exhibition (DATE). 268–273 M Balasubramanian, A Shrivastava
3 2022 Sparse and Low-bias Estimation of High Dimensional Vector Autoregressive Models T Ruiz, S Bhattacharyya, M Balasubramanian, K Bouchard
Learning for Dynamics and Control, 55-64, 2020
3 2020 Scaling of Union of Intersections for Inference of Granger Causal Networks from Observational Data M Balasubramanian, TD Ruiz, B Cook, M Prabhat, S Bhattacharyya, ...
2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS …, 2020
3 2020 Compiler Design for Accelerating Applications on Coarse-Grained Reconfigurable Architectures M Balasubramanian
Arizona State University, 2021
2 2021 Systems and methods for fast-mapping of coarse-grained reconfigurable arrays M Balasubramanian, A Shrivastava
US Patent App. 18/603,761, 2024
2024 Systems and methods for improved mapping of computational loops on reconfigurable architectures M Balasubramanian, A Shrivastava
US Patent 11,928,468, 2024
2024 
Aviral ShrivastavaArizona State UniversityAdresse e-mail validée de asu.edu
