| Cascade: Connecting rrams to extend analog dataflow in an end-to-end in-memory processing paradigm T Chou, W Tang, J Botimer, Z Zhang Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019 | 96 | 2019 |
| A 1.87-mm2 56.9-GOPS Accelerator for Solving Partial Differential Equations T Chen, J Botimer, T Chou, Z Zhang IEEE Journal of Solid-State Circuits 55 (6), 1709-1718, 2020 | 19 | 2020 |
| A 256Gb/s/mm-shoreline AIB-Compatible 16nm FinFET CMOS Chiplet for 2.5 D Integration with Stratix 10 FPGA on EMIB and Tiling on Silicon Interposer C Liu, J Botimer, Z Zhang 2021 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2021 | 17 | 2021 |
| Matrix Data Reuse Techniques in Processing Systems J Botimer, M Zidan, C Liu, F Meng, T Wesley, W Lu, Z Zhang US Patent App. 16/731,035, 2021 | 14 | 2021 |
| An SRAM-based accelerator for solving partial differential equations T Chen, J Botimer, T Chou, Z Zhang 2019 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2019 | 11 | 2019 |
| Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration W Tang, SG Cho, TT Hoang, J Botimer, WQ Zhu, CC Chang, CH Lu, J Zhu, ... IEEE Journal of Solid-State Circuits, 2023 | 4 | 2023 |
| Non-volatile memory based processors and dataflow techniques Z Zhang, M Zidan, F Meng, C Liu, J Botimer, T Wesley, W Lu US Patent 11,537,535, 2022 | 3 | 2022 |
| Inter-layer communication techniques for memory processing unit architectures J Botimer, M Zidan, C Liu, T Wesley, W Lu US Patent App. 17/943,143, 2023 | 2 | 2023 |
| Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm2 AIB 2.0 Interface to Provide Versatile Workload … W Tang, SG Cho, TT Hoang, J Botimer, WQ Zhu, CC Chang, CH Lu, J Zhu, ... 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2023 | 1 | 2023 |
| Core group memory processing with multi-precision weight packing J Botimer, M Zidan, T Wesley, C Liu, W Lu US Patent App. 18/368,493, 2024 | | 2024 |
| Core group memory processsing chip design T Wesley, J Botimer, M Zidan, C Liu, W Lu US Patent App. 18/534,487, 2024 | | 2024 |
| Direct dataflow compute-in-memory accelerator interface and architecture W Lu, K Kressin, M Zidan, J Botimer, T Wesley, C Liu US Patent App. 17/945,042, 2024 | | 2024 |
| Core group memory processsing with mac reuse M Zidan, J Botimer, T Wesly, C Liu, Z Zhang, W Lu US Patent App. 18/109,790, 2023 | | 2023 |
| Core group memory processing with group b-float encoding M Zidan, J Botimer, T Wesly, C Liu, Z Zhang, W Lu US Patent App. 18/109,788, 2023 | | 2023 |
| Core group memory processsing unit architectures and configurations M Zidan, J Botimer, T Wesly, C Liu, Z Zhang, W Lu US Patent App. 18/109,736, 2023 | | 2023 |
| Processing unit architectures and techniques for reusable instructions and data ZS Fu, WC Huang, CH Yang, Z Zhang, T Wesley, J Botimer US Patent App. 17/944,014, 2023 | | 2023 |
| Memory processing unit core architectures J Botimer, M Zidan, T Wesley, C Liu, W Lu US Patent App. 17/943,116, 2023 | | 2023 |
| Memory processing unit architecture mapping techniques M Zidan, J Botimer, T Wesley, C Liu, W Lu US Patent App. 17/943,119, 2023 | | 2023 |
| Memory processing unit architectures and configurations M Zidan, J Botimer, T Wesley, C Liu, Z Zhang, W Lu US Patent App. 17/943,100, 2023 | | 2023 |
| Memory processing unit architecture MA Zidan, JC Botimer, C Liu, F Meng, TA Wesley, Z Zhang, W Lu US Patent 11,488,650, 2022 | | 2022 |
