| Onsite matrix elements of the tight-binding Hamiltonian of a strained crystal: Application to silicon, germanium, and their alloys YM Niquet, D Rideau, C Tavernier, H Jaouen, X Blase Physical Review B—Condensed Matter and Materials Physics 79 (24), 245201, 2009 | 242 | 2009 |
| Transformer for integrated circuits M Marty, H Jaouen US Patent 6,031,445, 2000 | 201 | 2000 |
| Strained Si, Ge, and Si 1− x Ge x alloys modeled with a first-principles-optimized full-zone k∙ p method D Rideau, M Feraille, L Ciampolini, M Minondo, C Tavernier, H Jaouen, ... Physical Review B—Condensed Matter and Materials Physics 74 (19), 195208, 2006 | 195 | 2006 |
| Combined synchrotron x-ray diffraction and wafer curvature measurements during Ni–Si reactive film formation C Rivero, P Gergaud, M Gailhanou, O Thomas, B Froment, H Jaouen, ... Applied Physics Letters 87 (4), 2005 | 59 | 2005 |
| A new backscattering model giving a description of the quasi-ballistic transport in nano-MOSFET E Fuchs, P Dollfus, G Le Carval, S Barraud, D Villanueva, F Salvetti, ... IEEE transactions on electron devices 52 (10), 2280-2289, 2005 | 57 | 2005 |
| On the validity of the effective mass approximation and the Luttinger kp model in fully depleted SOI MOSFETs D Rideau, M Feraille, M Michaillat, YM Niquet, C Tavernier, H Jaouen Solid-State Electronics 53 (4), 452-461, 2009 | 38 | 2009 |
| LDMOS modeling for analog and RF circuit design A Canepari, G Bertrand, A Giry, M Minondo, F Blanchet, H Jaouen, ... Proceedings of 35th European Solid-State Device Research Conference, 2005 …, 2005 | 32 | 2005 |
| Random telegraph signal noise SPICE modeling for circuit simulators C Leyris, S Pilorget, M Marin, M Minondo, H Jaouen ESSDERC 2007-37th European Solid State Device Research Conference, 187-190, 2007 | 29 | 2007 |
| In situ study of stress evolution during the reaction of a nickel film with a silicon substrate C Rivero, P Gergaud, O Thomas, B Froment, H Jaouen Microelectronic engineering 76 (1-4), 318-323, 2004 | 29 | 2004 |
| On the accuracy of current TCAD hot carrier injection models in nanoscale devices A Zaka, Q Rafhay, M Iellina, P Palestri, R Clerc, D Rideau, D Garetto, ... Solid-state electronics 54 (12), 1669-1674, 2010 | 24 | 2010 |
| Analysis of defect capture cross sections using non-radiative multiphonon-assisted trapping model D Garetto, YM Randriamihaja, A Zaka, D Rideau, A Schmid, H Jaouen, ... Solid-state electronics 71, 74-79, 2012 | 22 | 2012 |
| The importance of the spacer region to explain short channels mobility collapse in 28nm Bulk and FDSOI technologies F Monsieur, Y Denis, D Rideau, V Quenette, G Gouget, C Tavernier, ... 2014 44th European Solid State Device Research Conference (ESSDERC), 254-257, 2014 | 20 | 2014 |
| Revisited RF compact model of gate resistance suitable for high-k/metal gate technology B Dormieu, P Scheer, C Charbuillet, H Jaouen, F Danneville IEEE Transactions on Electron Devices 60 (1), 13-19, 2012 | 20 | 2012 |
| FEM-based method to determine mechanical stress evolution during process flow in microelectronics. Application to stress-voiding S Orain, JC Barbé, X Federspiel, P Legallo, H Jaouen 5th International Conference on Thermal and Mechanical Simulation and …, 2004 | 20 | 2004 |
| Semiconductor device having separated exchange means H Jaouen, M Marty US Patent 6,081,030, 2000 | 19 | 2000 |
| Electronic transport investigation of arsenic‐implanted silicon. II. Annealing kinetics of defects C Christofides, G Ghibaudo, H Jaouen Journal of applied physics 65 (12), 4840-4844, 1989 | 17 | 1989 |
| Lateral operation bipolar transistor and a corresponding fabrication process O Menut, H Jaouen US Patent 6,897,545, 2005 | 16 | 2005 |
| Multi-scale strategy for high-k/metal-gate UTBB-FDSOI devices modeling with emphasis on back bias impact on mobility O Nier, D Rideau, YM Niquet, F Monsieur, VH Nguyen, F Triozon, A Cros, ... Journal of Computational Electronics 12, 675-684, 2013 | 15 | 2013 |
| Modeling stressed MOS oxides using a multiphonon-assisted quantum approach—Part II: transient effects D Garetto, YM Randriamihaja, D Rideau, A Zaka, A Schmid, Y Leblebici, ... IEEE transactions on electron devices 59 (3), 621-630, 2012 | 14 | 2012 |
| Investigations of stress sensitivity of 0.12 CMOS technology using process modeling V Senez, T Hoffmann, E Robilliart, G Bouche, H Jaouen, M Lunenborg, ... International Electron Devices Meeting. Technical Digest (Cat. No. 01CH37224 …, 2001 | 14 | 2001 |