| A Passive UHF RF Identification CMOS Tag IC Using Ferroelectric RAM in 0.35- Technology H Nakamoto, D Yamazaki, T Yamamoto, H Kurata, S Yamada, K Mukaida, ... IEEE Journal of Solid-State Circuits 42 (1), 101-110, 2006 | 393 | 2006 |
| A zero-IF 60 GHz 65 nm CMOS transceiver with direct BPSK modulation demonstrating up to 6 Gb/s data rates over a 2 m wireless link A Tomkins, RA Aroca, T Yamamoto, ST Nicolson, Y Doi, SP Voinigescu IEEE journal of solid-state circuits 44 (8), 2085-2099, 2009 | 203 | 2009 |
| A passive UHF RFID tag LSI with 36.6% efficiency CMOS-only rectifier and current-mode demodulator in 0.35/spl mu/m FeRAM technology H Nakamoto, D Yamazaki, T Yamamoto, H Kurata, S Yamada, K Mukaida, ... 2006 IEEE International Solid State Circuits Conference-Digest of Technical …, 2006 | 124 | 2006 |
| A fasting-responsive signaling pathway that extends life span in C. elegans M Uno, S Honjoh, M Matsuda, H Hoshikawa, S Kishimoto, T Yamamoto, ... Cell reports 3 (1), 79-91, 2013 | 119 | 2013 |
| Optical modulation apparatus and method of controlling optical modulator H Ooi, H Nakamoto, G Ishikawa, T Yamamoto, Y Nishizawa US Patent 6,362,913, 2002 | 106 | 2002 |
| 22.2 A 25Gb/s hybrid integrated silicon photonic transceiver in 28nm CMOS and SOI Y Chen, M Kibune, A Toda, A Hayakawa, T Akiyama, S Sekiguchi, H Ebe, ... 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 102 | 2015 |
| 40Gb/s 4: 1 MUX/1: 4 DEMUX in 90nm standard CMOS K Kanda, D Yamazaki, T Yamamoto, M Horinaka, J Ogawa, H Tamura, ... ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State …, 2005 | 97 | 2005 |
| Phase I/II study of adding intraperitoneal paclitaxel in patients with pancreatic cancer and peritoneal metastasis S Yamada, T Fujii, T Yamamoto, H Takami, I Yoshioka, S Yamaki, ... Journal of British Surgery 107 (13), 1811-1817, 2020 | 53 | 2020 |
| A single-40 Gb/s dual-20 Gb/s serializer IC with SFI-5.2 interface in 65 nm CMOS K Kanda, H Tamura, T Yamamoto, S Matsubara, M Kibune, Y Doi, ... IEEE Journal of Solid-State Circuits 44 (12), 3580-3589, 2009 | 47 | 2009 |
| A zero-IF 60GHz transceiver in 65nm CMOS with≫ 3.5 Gb/s links A Tomkins, RA Aroca, T Yamamoto, ST Nicolson, Y Doi, SP Voinigescu 2008 IEEE Custom Integrated Circuits Conference, 471-474, 2008 | 45 | 2008 |
| A 60-GHz 1.65 mW 25.9% locking range multi-order LC oscillator based injection locked frequency divider in 65nm CMOS K Takatsu, H Tamura, T Yamamoto, Y Doi, K Kanda, T Shibasaki, ... IEEE Custom Integrated Circuits Conference 2010, 1-4, 2010 | 43 | 2010 |
| Low-driving-current temperature-stable 10 Gbit/s operation of p-doped 1.3 µm quantum dot lasers between 20 and 90° C M Ishida, N Hatori, K Otsubo, T Yamamoto, Y Nakata, H Ebe, M Sugawara, ... Electronics Letters 43 (4), 219-221, 2007 | 43 | 2007 |
| 10 Gbit/s optical front end using Si-bipolar preamplifier IC, flipchip APD, and slant-end fibre H Hamano, T Yamamoto, Y Nishizawa, Y Oikawa, H Kuwatsuka, A Tahara, ... Electronics Letters 27 (18), 1602-1605, 1991 | 43 | 1991 |
| Method of producing an electronic circuit package Y Arai, H Hamano, I Amemiya, T Yamamoto, T Ihara US Patent 5,206,986, 1993 | 39 | 1993 |
| A 3 Watt 39.8–44.6 Gb/s dual-mode SFI5. 2 SerDes chip set in 65 nm CMOS N Nedovic, A Kristensson, S Parikh, S Reddy, S McLeod, N Tzartzanis, ... IEEE journal of solid-state circuits 45 (10), 2016-2029, 2010 | 35 | 2010 |
| Optical modulation apparatus and method of controlling H Ooi, H Nakamoto, G Ishikawa, T Yamamoto, Y Nishizawa US Patent 6,278,539, 2001 | 35 | 2001 |
| Effects of time zone changes on sleep-west-east flight and east-west flight S Endo, T Yamamoto, M Sasaki | 32 | 1978 |
| IEEE International Solid-State Circuits Conference Y Chen, M Kibune, A Toda, A Hayakawa, T Akiyama, S Sekiguchi, H Ebe, ... IEEE,, 2015 | 31 | 2015 |
| Uncooled, low-driving-current 25.8 Gbit/s direct modulation using 1.3 µm AlGaInAs MQW distributed-reflector lasers M Matsuda, T Simoyama, A Uetake, S Okumura, M Ekawa, T Yamamoto Electronics letters 48 (8), 450-452, 2012 | 28 | 2012 |
| Interposer for integrated circuit chip package M Lee, T Yamamoto US Patent 9,496,248, 2016 | 27 | 2016 |
