| Transport-triggered soft cores P Jääskeläinen, A Tervo, GP Vayá, T Viitanen, N Behmann, J Takala, ... 2018 IEEE International Parallel and Distributed Processing Symposium …, 2018 | 29 | 2018 |
| Performance monitoring for automatic speech recognition in noisy multi-channel environments BT Meyer, SH Mallidi, AMC Martinez, G Payá-Vayá, H Kayser, ... 2016 IEEE Spoken Language Technology Workshop (SLT), 50-56, 2016 | 23 | 2016 |
| DNN-based performance measures for predicting error rates in automatic speech recognition and optimizing hearing aid parameters AMC Martinez, L Gerlach, G Payá-Vayá, H Hermansky, J Ooster, ... Speech Communication 106, 44-56, 2019 | 22 | 2019 |
| VLIW architecture optimization for an efficient computation of stereoscopic video applications G Payá-Vayá, J Martín-Langerwerf, C Banz, F Giesemann, P Pirsch, ... The 2010 International Conference on Green Circuits and Systems, 457-462, 2010 | 20 | 2010 |
| Coherent design of hybrid approximate adders: Unified design framework and metrics A Najafi, M Weißbrich, G Payá-Vayá, A Garcia-Ortiz IEEE Journal on Emerging and Selected Topics in Circuits and Systems 8 (4 …, 2018 | 19 | 2018 |
| A fair comparison of adders in stochastic regime A Najafi, M Weißbrich, GP Vayá, A Garcia-Ortiz 2017 27th International Symposium on Power and Timing Modeling, Optimization …, 2017 | 19 | 2017 |
| Customizing a vliw-simd application-specific instruction-set processor for hearing aid devices J Hartig, L Gerlach, G Payá-Vayá, H Blume 2014 IEEE Workshop on Signal Processing Systems (SiPS), 1-6, 2014 | 16 | 2014 |
| A survey on application specific processor architectures for digital hearing aids L Gerlach, G Paya-Vaya, H Blume Journal of Signal Processing Systems, 1-16, 2022 | 15 | 2022 |
| Towards a common software/hardware methodology for future advanced driver assistance systems G Payá-Vayá, H Blume Taylor & Francis, 2017 | 14 | 2017 |
| An area efficient real-and complex-valued multiply-accumulate SIMD unit for digital signal processors L Gerlach, G Payá-Vayá, H Blume 2015 IEEE Workshop on Signal Processing Systems (SiPS), 1-6, 2015 | 14 | 2015 |
| Evolutionary algorithms for instruction scheduling, operation merging, and register allocation in VLIW compilers F Giesemann, L Gerlach, G Paya-Vaya Journal of Signal Processing Systems 92 (7), 655-678, 2020 | 13 | 2020 |
| 2D-DCT on FPGA by polynomial transformation in two-dimensions AM Patiño, MM Peiró, F Ballester, G Paya 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No …, 2004 | 13 | 2004 |
| Kavuaka: A low power application specific hearing aid processor L Gerlach, G Paya-Vaya, H Blume 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration …, 2019 | 12 | 2019 |
| Performance evaluation of the Intel Xeon Phi manycore architecture using parallel video-based driver assistance algorithms OJ Arndt, D Becker, F Giesemann, G Payá-Vayá, C Bartels, H Blume 2014 International Conference on Embedded Computer Systems: Architectures …, 2014 | 12 | 2014 |
| Dynamic data-path self-reconfiguration of a VLIW-SIMD soft-processor architecture G Payá-Vayá, R Burg, H Blume Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 26, 2012 | 12 | 2012 |
| Design and Analysis of a Generic VLIW Processor for Multimedia Applications G Payá-Vayá Diss. Institute of Microelectronic Systems, Leibniz Universität Hannover, 2011 | 12 | 2011 |
| A multi-shared register file structure for VLIW processors G Payá-Vayá, J Martín-Langerwerf, P Pirsch Journal of Signal Processing Systems 58, 215-231, 2010 | 12 | 2010 |
| Design space exploration of media processors: A parameterized scheduler G Paya-Vaya, J Martin-Langerwerf, P Taptimthong, P Pirsch 2007 international conference on embedded computer systems: Architectures …, 2007 | 12 | 2007 |
| Evaluation of different processor architecture organizations for on-site electronics in harsh environments S Gesper, M Weißbrich, T Stuckenberg, P Jääskeläinen, H Blume, ... International Journal of Parallel Programming 49 (4), 541-569, 2021 | 11 | 2021 |
| Cross-layer fault-space pruning for hardware-assisted fault injection C Dietrich, A Schmider, O Pusz, GP Vayá, D Lohmann Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 10 | 2018 |
Florian GiesemannUniversität HannoverDirección de correo verificada de ims.uni-hannover.de
