Bandstructure effects in silicon nanowire electron transport N Neophytou, A Paul, MS Lundstrom, G Klimeck IEEE Transactions on Electron Devices 55 (6), 1286-1297, 2008 | 219 | 2008 |
Spin-based computing: Device concepts, current status, and a case study on a high-performance microprocessor J Kim, A Paul, PA Crowell, SJ Koester, SS Sapatnekar, JP Wang, CH Kim Proceedings of the IEEE 103 (1), 106-130, 2014 | 186 | 2014 |
A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI KI Seo, B Haran, D Gupta, D Guo, T Standaert, R Xie, H Shang, E Alptekin, ... 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical …, 2014 | 111 | 2014 |
Full three-dimensional quantum transport simulation of atomistic interface roughness in silicon nanowire FETs SG Kim, M Luisier, A Paul, TB Boykin, G Klimeck IEEE Transactions on Electron Devices 58 (5), 1371-1380, 2011 | 77 | 2011 |
Modified valence force field approach for phonon dispersion: from zinc-blende bulk to nanowires: Methodology and computational details A Paul, M Luisier, G Klimeck Journal of computational electronics 9, 160-172, 2010 | 77 | 2010 |
Effects of deposition parameters on the properties of chromium carbide coatings deposited onto steel by sputtering A Paul, J Lim, K Choi, C Lee Materials Science and Engineering: A 332 (1-2), 123-128, 2002 | 68 | 2002 |
Bandstructure effects in silicon nanowire hole transport N Neophytou, A Paul, G Klimeck IEEE Transactions on Nanotechnology 7 (6), 710-719, 2008 | 67 | 2008 |
Simulations of nanowire transistors: Atomistic vs. effective mass models N Neophytou, A Paul, MS Lundstrom, G Klimeck Journal of Computational Electronics 7, 363-366, 2008 | 45 | 2008 |
Atomistic approach to alloy scattering in Si1− xGex SR Mehrotra, A Paul, G Klimeck Applied Physics Letters 98 (17), 2011 | 42 | 2011 |
FinFET channel stress using tungsten contacts in raised epitaxial source and drain A Paul, A Bello, VK Kamineni, D Deniz US Patent 8,975,142, 2015 | 38 | 2015 |
Enhanced valence force field model for the lattice properties of gallium arsenide S Steiger, M Salmani-Jelodar, D Areshkin, A Paul, T Kubis, M Povolotskyi, ... Physical Review B—Condensed Matter and Materials Physics 84 (15), 155204, 2011 | 38 | 2011 |
Comprehensive study of effective current variability and MOSFET parameter correlations in 14nm multi-Fin SOI FINFETs A Paul, A Bryant, TB Hook, CC Yeh, V Kamineni, JB Johnson, N Tripathi, ... Electron Devices Meeting (IEDM), 2013 IEEE International, 13.5. 1-13.5. 4, 2013 | 36 | 2013 |
Comprehensive simulation of program, erase and retention in charge trapping flash memories A Paul, C Sridhar, S Gedam, S Mahapatra 2006 International Electron Devices Meeting, 1-4, 2006 | 33 | 2006 |
Methods of forming stressed multilayer FinFET devices with alternative channel materials A Paul, AP Jacob, MH Chi US Patent 9,023,705, 2015 | 31 | 2015 |
Performance prediction of ultrascaled SiGe/Si core/shell electron and hole nanowire MOSFETs A Paul, S Mehrotra, M Luisier, G Klimeck IEEE electron device letters 31 (4), 278-280, 2010 | 31 | 2010 |
Atomistic study of electronic structure of PbSe nanowires A Paul, G Klimeck Applied Physics Letters 98 (21), 2011 | 27 | 2011 |
Intrinsic reliability improvement in biaxially strained SiGe p-MOSFETs S Deora, A Paul, R Bijesh, J Huang, G Klimeck, G Bersuker, PD Krisch, ... IEEE electron device letters 32 (3), 255-257, 2011 | 25 | 2011 |
On the validity of the top of the barrier quantum transport model for ballistic nanowire MOSFETs A Paul, S Mehrotra, G Klimeck, M Luisier 2009 13th International Workshop on Computational Electronics, 1-4, 2009 | 25 | 2009 |
FinFET with multilayer fins for multi-value logic (MVL) applications and method of forming MH Chi, A Jacob, A Paul US Patent 9,362,277, 2016 | 22 | 2016 |
Band structure lab A Paul, M Luisier, N Neophytou, R Kim, J Geng, M McLennan, ... doi, 2006 | 22 | 2006 |