Matthew Mattina

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Paul N WhatmoughQualcomm AI Research, Harvard UniversityDirección de correo verificada de qti.qualcomm.com
David WentzlaffAssociate Professor of Electrical Engineering, Princeton UniversityDirección de correo verificada de princeton.edu
Carl RameyArchitect, IntelDirección de correo verificada de intel.com
Yuhao ZhuUniversity of RochesterDirección de correo verificada de rochester.edu
Ananda SamajdarStaff Research Scientist, IBM ResearchDirección de correo verificada de ibm.com
Ramon MatasPrincipal engineer @ nvidiaDirección de correo verificada de nvidia.com
Henry HoffmannLiew Family Chair of Computer Science, University of ChicagoDirección de correo verificada de cs.uchicago.edu
Joel EmerProfessor of the Practice, MIT - Sr. Distinguished Research Scientist, NvidiaDirección de correo verificada de csail.mit.edu
Aamer JaleelArchitecture Research Group (ARG), Nvidia ResearchDirección de correo verificada de nvidia.com
Toni JuanAssociate Professort, Computer Architecture Department, UPCDirección de correo verificada de ac.upc.edu
Seznec AndreINRIA/IRISADirección de correo verificada de inria.fr
Robert PeharzAssistant Professor of AI, TU GrazDirección de correo verificada de tugraz.at
Zoubin GhahramaniProfessor, University of Cambridge, and Distinguished Researcher, GoogleDirección de correo verificada de eng.cam.ac.uk
Mark EmbrechtsChief Science Officer, CardioMag Imaging, Inc. and Professor of Mechanical Aerospace and NuclearDirección de correo verificada de rpi.edu

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Matthew Mattina

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Dirección de correo verificada de alumni.princeton.edu

Machine learning artificial intelligence


Título Ordenar por citas Ordenar por año Ordenar por título	Citado por Citado por	Año
On-chip interconnection architecture of the tile processor D Wentzlaff, P Griffin, H Hoffmann, L Bao, B Edwards, C Ramey, ... IEEE micro 27 (5), 15-31, 2007	1241	2007
Tile64-processor: A 64-core soc with mesh interconnect S Bell, B Edwards, J Amann, R Conlin, K Joyce, V Leung, J MacKay, ... 2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008	857	2008
Federated learning based on dynamic regularization DAE Acar, Y Zhao, RM Navarro, M Mattina, PN Whatmough, V Saligrama arXiv preprint arXiv:2111.04263, 2021	838	2021
Computing in parallel processing environments PR Griffin, M Hostetter, A Agarwal, CC Miao, CD Metcalf, B Edwards, ... US Patent 8,738,860, 2014	416	2014
Scale-sim: Systolic cnn accelerator simulator A Samajdar, Y Zhu, P Whatmough, M Mattina, T Krishna arXiv preprint arXiv:1811.02883, 2018	315	2018
Micronets: Neural network architectures for deploying tinyml applications on commodity microcontrollers C Banbury, C Zhou, I Fedorov, R Matas, U Thakker, D Gope, ... Proceedings of machine learning and systems 3, 517-532, 2021	272	2021
A systematic methodology for characterizing scalability of dnn accelerators using scale-sim A Samajdar, JM Joseph, Y Zhu, P Whatmough, M Mattina, T Krishna 2020 IEEE International Symposium on Performance Analysis of Systems and …, 2020	193	2020
Sparse: Sparse architecture search for cnns on resource-constrained microcontrollers I Fedorov, RP Adams, M Mattina, P Whatmough Advances in Neural Information Processing Systems 32, 2019	191	2019
Last level cache (llc) performance of data mining workloads on a cmp-a case study of parallel bioinformatics workloads A Jaleel, M Mattina, B Jacob The Twelfth International Symposium on High-Performance Computer …, 2006	179	2006
Tarantula: a vector extension to the alpha architecture R Espasa, F Ardanaz, J Emer, S Felix, J Gago, R Gramunt, I Hernandez, ... ACM SIGARCH Computer Architecture News 30 (2), 281-292, 2002	151	2002
High performance, scalable multi chip interconnect CG Ramey, M Mattina US Patent 9,424,228, 2016	132	2016
Caching in multicore and multiprocessor architectures A Agarwal, IR Bratt, M Mattina US Patent 7,805,575, 2010	119	2010
Euphrates: Algorithm-soc co-design for low-power mobile continuous vision Y Zhu, A Samajdar, M Mattina, P Whatmough arXiv preprint arXiv:1803.11232, 2018	111	2018
TinyLSTMs: Efficient neural speech enhancement for hearing aids I Fedorov, M Stamenovic, C Jensen, LC Yang, A Mandell, Y Gan, ... arXiv preprint arXiv:2005.11138, 2020	108	2020
Scale-sim: Systolic CNN accelerator A Samajdar, Y Zhu, PN Whatmough, M Mattina, T Krishna CoRR, 2018	89	2018
Systolic tensor array: An efficient structured-sparse GEMM accelerator for mobile CNN inference ZG Liu, PN Whatmough, M Mattina IEEE Computer Architecture Letters 19 (1), 34-37, 2020	88	2020
Managing cache memory in a parallel processing environment D Wentzlaff, M Mattina, A Agarwal US Patent 7,882,307, 2011	86	2011
Debiasing model updates for improving personalized federated training DAE Acar, Y Zhao, R Zhu, R Matas, M Mattina, P Whatmough, ... International conference on machine learning, 21-31, 2021	76	2021
S2ta: Exploiting structured sparsity for energy-efficient mobile cnn acceleration ZG Liu, PN Whatmough, Y Zhu, M Mattina 2022 IEEE International Symposium on High-Performance Computer Architecture …, 2022	75	2022
Mapping memory in a parallel processing environment D Wentzlaff, M Mattina, A Agarwal US Patent 7,620,791, 2009	65	2009

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