| Graph-learning-driven path-based timing analysis results predictor from graph-based timing analysis Y Ye, T Chen, Y Gao, H Yan, B Yu, L Shi Proceedings of the 28th Asia and South Pacific Design Automation Conference …, 2023 | 14 | 2023 |
| Fast and accurate wire timing estimation based on graph learning Y Ye, T Chen, Y Gao, H Yan, B Yu, L Shi 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2023 | 11 | 2023 |
| Fast and accurate aging-aware cell timing model via graph learning Y Ye, T Chen, Z Wang, H Yan, B Yu, L Shi IEEE Transactions on Circuits and Systems II: Express Briefs, 2023 | 7 | 2023 |
| Aging-Aware Critical Path Selection via Graph Attention Networks Y Ye, T Chen, Y Gao, H Yan, B Yu, L Shi IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2023 | 5 | 2023 |
| Timing-Driven Technology Mapping Approximation Based on Reinforcement Learning Y Ye, T Chen, Y Gao, H Yan, B Yu, L Shi IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024 | 2 | 2024 |
| ARS-Flow: A Design Space Exploration Flow for Accelerator-rich System based on Active Learning S Huang, Y Ye, H Yan, L Shi 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC), 213-218, 2024 | 2 | 2024 |
| Optimized matrix ordering of sparse linear solver using a few-shot model for circuit simulation Q Chen, Y Ye, M Li, H Yan, L Shi Integration 93, 102062, 2023 | 2 | 2023 |
| GNN-based TICER for RC Reduction on Large-scale Interconnect L Tian, Y Ye, H Yan 2022 IEEE 16th International Conference on Solid-State & Integrated Circuit …, 2022 | 2 | 2022 |
| Learning-driven Physically-aware Large-scale Circuit Gate Sizing Y Ye, P Xu, L Ren, T Chen, H Yan, B Yu, L Shi arXiv preprint arXiv:2403.08193, 2024 | 1 | 2024 |
| FPGNN-ATPG: An Efficient Fault Parallel Automatic Test Pattern Generator Y Ye, Z Wang, Z Xue, Z Wang, Y Gao, H Yan Proceedings of the Great Lakes Symposium on VLSI 2023, 299-304, 2023 | 1 | 2023 |
| Fast and Accurate Electromigration Analysis of Multi-Segment Wires Y Zuo, Y Ye, H Yan, L Shi 2023 International Symposium of Electronics Design Automation (ISEDA), 340-344, 2023 | 1 | 2023 |
| Timing-driven Approximate Logic Synthesis Based on Double-chase Grey Wolf Optimizer X Hu, Y Ye, T Chen, H Yan, B Yu arXiv preprint arXiv:2411.10990, 2024 | | 2024 |
| RankTuner: When Design Tool Parameter Tuning Meets Preference Bayesian Optimization P Xu, S Zheng, Y Ye, C Bai, S Xu, H Geng, TY Ho, B Yu | | 2024 |
| Aging-Aware Logic Restructure Acceleration Based on Heterogeneous Graph Learning Z Xue, Y Liu, Y Ye, T Chen, H Yan, L Shi 2024 2nd International Symposium of Electronics Design Automation (ISEDA …, 2024 | | 2024 |
| A Graph-Learning-Driven Prediction Method for Combined Electromigration and Thermomigration Stress on Multi-Segment Interconnects Y Zuo, Y Ye, H Zhang, T Chen, H Yan, L Shi 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2024 | | 2024 |
| Heterogeneous Graph Attention Network Based Statistical Timing Library Characterization with Parasitic RC Reduction X Cheng, Y Ye, G He, Q Song, P Cao 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC), 171-176, 2024 | | 2024 |
| An Optimization-aware Pre-Routing Timing Prediction Framework Based on Heterogeneous Graph Learning G He, W Ding, Y Ye, X Cheng, Q Song, P Cao 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC), 177-182, 2024 | | 2024 |
Tinghuan ChenThe Chinese University of Hong Kong, ShenzhenDirección de correo verificada de cuhk.edu.cn