| Integrating receiver with precharge circuitry JL Zerbe, BW Garlepp, PS Chau, KS Donnelly, MA Horowitz, ... US Patent 8,199,859, 2012 | 527 | 2012 |
| Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell JL Zerbe, CW Werner, V Stojanovic, F Chen, J Wei, G Tsang, D Kim, ... IEEE Journal of Solid-State Circuits 38 (12), 2121-2130, 2003 | 360 | 2003 |
| Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery V Stojanovic, A Ho, BW Garlepp, F Chen, J Wei, G Tsang, E Alon, ... IEEE Journal of Solid-State Circuits 40 (4), 1012-1026, 2005 | 219 | 2005 |
| Techniques for improved timing control of memory devices FA Ware, C Werner, I Shaeffer US Patent App. 12/596,360, 2010 | 169 | 2010 |
| Signaling system with selectively-inhibited adaptive equalization CW Werner, A Ho US Patent 7,715,471, 2010 | 167 | 2010 |
| Transparent multi-mode PAM interface JL Zerbe, CW Werner, WF Stonecypher, FF Chen US Patent 7,308,058, 2007 | 145 | 2007 |
| Coded differential intersymbol interference reduction A Amirkhany, A Abbasfar, K Kaviani, W Beyene, C Werner US Patent 9,165,615, 2015 | 128 | 2015 |
| Frequency responsive bus coding JM Wilson, A Abbasfar, J Eble III, L Luo, JM Kizer, CW Werner, W Dettloff US Patent 8,498,344, 2013 | 128 | 2013 |
| Adaptive equalization and data recovery in a dual-mode (PAM2/4) serial link transceiver V Stojanovic, A Ho, B Garlepp, F Chen, J Wei, E Alon, C Werner, J Zerbe, ... 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No …, 2004 | 109 | 2004 |
| Charge pump circuit adjustable in response to an external voltage source AM Haeberli, SC Wong, HC So, CW Werner, CYM Wang, LSJ Wong US Patent 6,370,075, 2002 | 106 | 2002 |
| Method and apparatus for calibrating a multi-level current mode driver C Werner, M Horowitz, P Chau, S Best, S Sidiropoulos US Patent 6,772,351, 2004 | 96 | 2004 |
| Adjustable level shifter circuits for analog or multilevel memories AM Haeberli, CW Werner, CYM Wang, HC So, LSJ Wong, SC Wong US Patent 6,184,726, 2001 | 92 | 2001 |
| Charge pump circuit adjustable in response to an external voltage source AM Haeberli, SC Wong, HC So, CW Werner, CYM Wang, LSJ Wong US Patent 6,760,262, 2004 | 89 | 2004 |
| Low latency multi-level communication interface JL Zerbe, BW Garlepp, PS Chau, KS Donnelly, MA Horowitz, ... US Patent 7,626,442, 2009 | 88 | 2009 |
| Method and apparatus for calibrating a multi-level current mode driver having a plurality of source calibration signals C Werner, M Horowitz, P Chau, S Best, S Sidiropoulos US Patent 7,456,778, 2008 | 81 | 2008 |
| Integrated circuit with analog or multilevel storage cells and user-selectable sampling frequency CW Werner, AM Haeberli, LSJ Wong, CYM Wang, HC So, SC Wong US Patent 7,298,670, 2007 | 80 | 2007 |
| 1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus JL Zerbe, PS Chau, CW Werner, TP Thrush, HJ Liaw, BW Garlepp, ... IEEE Journal of Solid-State Circuits 36 (5), 752-760, 2001 | 80 | 2001 |
| A 2 Gb/s/pin 4-PAM parallel bus interface with transmit crosstalk cancellation, equalization, and integrating receivers JL Zerbe, PS Chau, CW Werner, WF Stonecypher, HJ Liaw, GJ Yeh, ... 2001 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2001 | 80 | 2001 |
| Session management for communication in a heterogeneous network RM Goudarzi, JK Thomas, I Georgiadis, MJ Grimse, CW Werner US Patent App. 13/996,449, 2013 | 75 | 2013 |
| Adjustable circuits for analog or multi-level memory AM Haeberli, SC Wong, HC So, CW Werner, CYM Wang, LSJ Wong US Patent 6,556,465, 2003 | 73 | 2003 |