Jingsheng Jason Cong

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Glenn ReinmanProfessor of Computer Science, UCLADirección de correo verificada de cs.ucla.edu
Zhiru ZhangCornell UniversityDirección de correo verificada de cornell.edu
Deming ChenAbel Bliss Professor. University of Illinois at Urbana-ChampaignDirección de correo verificada de illinois.edu
Bingjun XiaoUCLADirección de correo verificada de cs.ucla.edu
Zhenman FangAssistant Professor, Simon Fraser UniversityDirección de correo verificada de sfu.ca
Guojie LuoPeking UniversityDirección de correo verificada de pku.edu.cn
Guangyu SunSchool of Integrated Circuits, Peking UniversityDirección de correo verificada de pku.edu.cn
Peng LiPostDoc of Computer Science, UCLADirección de correo verificada de cs.ucla.edu
Peng ZhangComputer Science, University of Califronia, Los AngelesDirección de correo verificada de cs.ucla.edu
Yiping FanXilinx Inc., AutoESL, UCLADirección de correo verificada de cs.ucla.edu
YI ZOUUniversity of California Los AngeelsDirección de correo verificada de cs.ucla.edu
Peng WeiUniversity of California, Los AngelesDirección de correo verificada de cs.ucla.edu
Peipei ZhouAssistant Professor, Brown UniversityDirección de correo verificada de brown.edu
David Z. PanProfessor, Silicon Labs Endowed Chair, ECE Dept., University of Texas at AustinDirección de correo verificada de ece.utexas.edu
Lei HeProfessor of Electric Engineering, University of California, Los AngelesDirección de correo verificada de ee.ucla.edu
Cody (Hao) YuSoftware Engineer @ Anyscale | ex-Amazonian | UCLA PhD ‘19Dirección de correo verificada de anyscale.com
Chen ZhangShanghai Jiao Tong UniversityDirección de correo verificada de sjtu.edu.cn
Mau-Chung Frank ChangUniversity of California, Los AngelesDirección de correo verificada de ee.ucla.edu
Karthik GururajUniversity of California Los Angeles, Intel CorpDirección de correo verificada de intel.com
Yun (Eric) LiangProfessor of EECS, Peking University, ACM Distinguished ScientistDirección de correo verificada de pku.edu.cn

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Jingsheng Jason Cong

Volgenau Chair for Engineering Excellence, Computer Science and Electrical Engineering, University

Dirección de correo verificada de cs.ucla.edu - Página principal

customized computing FPGA electronic design automation quantum computing


Título Ordenar por citas Ordenar por año Ordenar por título	Citado por Citado por	Año
Optimizing FPGA-based accelerator design for deep convolutional neural networks C Zhang, P Li, G Sun, Y Guan, B Xiao, J Cong Proceedings of the 2015 ACM/SIGDA international symposium on field …, 2015	2532	2015
High-Level Synthesis for FPGAs: From Prototyping to Deployment Cong	1051*
FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs J Cong, Y Ding IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1994	849	1994
Caffeine: Toward uniformed representation and acceleration for deep convolutional neural networks C Zhang, G Sun, Z Fang, P Zhou, P Pan, J Cong IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018	719	2018
A thermal-driven floorplanning algorithm for 3D ICs J Cong, J Wei, Y Zhang IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004 …, 2004	565	2004
Minimizing computation in convolutional neural networks J Cong, B Xiao International conference on artificial neural networks, 281-290, 2014	488	2014
Automated systolic array architecture synthesis for high throughput CNN inference on FPGAs X Wei, CH Yu, P Zhang, Y Chen, Y Wang, H Hu, Y Liang, J Cong Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017	484	2017
Scaling for edge inference of deep neural networks X Xu, Y Ding, SX Hu, M Niemier, J Cong, Y Hu, Y Shi Nature Electronics 1 (4), 216-222, 2018	429	2018
Performance optimization of VLSI interconnect layout J Cong, L He, CK Koh, PH Madden Integration 21 (1-2), 1-94, 1996	413	1996
FP-DNN: An automated framework for mapping deep neural networks onto FPGAs with RTL-HLS hybrid templates Y Guan, H Liang, N Xu, W Wang, S Shi, X Chen, G Sun, W Zhang, J Cong 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom …, 2017	406	2017
CMP network-on-chip overlaid with multi-band RF-interconnect MF Chang, J Cong, A Kaplan, M Naik, G Reinman, E Socher, SW Tam 2008 IEEE 14th International Symposium on High Performance Computer …, 2008	366	2008
Application-specific instruction generation for configurable processor architectures J Cong, Y Fan, G Han, Z Zhang Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field …, 2004	308	2004
SACNN: Self-attention convolutional neural network for low-dose CT denoising with self-supervised perceptual loss network M Li, W Hsu, X Xie, J Cong, W Gao IEEE transactions on medical imaging 39 (7), 2289-2301, 2020	293	2020
Combinational logic synthesis for LUT based field programmable gate arrays J Cong, Y Ding ACM Transactions on Design Automation of Electronic Systems (TODAES) 1 (2 …, 1996	290	1996
Provably good performance-driven global routing J Cong, AB Kahng, G Robins, M Sarrafzadeh, CK Wong IEEE transactions on computer-aided design of integrated circuits and …, 1992	287	1992
On area/depth trade-off in LUT-based FPGA technology mapping J Cong, Y Ding Proceedings of the 30th International Design Automation Conference, 213-218, 1993	286	1993
An interconnect-centric design flow for nanometer technologies J Cong Proceedings of the IEEE 89 (4), 505-528, 2001	280	2001
Energy-efficient CNN implementation on a deeply pipelined FPGA cluster C Zhang, D Wu, J Sun, G Sun, G Luo, J Cong Proceedings of the 2016 International Symposium on Low Power Electronics and …, 2016	273	2016
mPL6: Enhanced multilevel mixed-size placement TF Chan, J Cong, JR Shinnerl, K Sze, M Xie Proceedings of the 2006 international symposium on Physical design, 212-214, 2006	272	2006
A scalable micro wireless interconnect structure for CMPs SB Lee, SW Tam, I Pefkianakis, S Lu, MF Chang, C Guo, G Reinman, ... Proceedings of the 15th annual international conference on Mobile computing …, 2009	270	2009

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