| Multi-level cell STT-RAM: Is it realistic or just a dream? Y Zhang, L Zhang, W Wen, G Sun, Y Chen Proceedings of the International Conference on Computer-Aided Design, 526-532, 2012 | 115 | 2012 |
| Asymmetry of MTJ switching and its implication to STT-RAM designs Y Zhang, X Wang, Y Li, AK Jones, Y Chen 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2012 | 107 | 2012 |
| A 1.041-Mb/mm2 27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation … B Yan, JL Hsu, PC Yu, CC Lee, Y Zhang, W Yue, G Mei, Y Yang, Y Yang, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 188-190, 2022 | 101 | 2022 |
| STT-RAM cell design optimization for persistent and non-persistent error rate reduction: A statistical design view Y Zhang, X Wang, Y Chen 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 471-477, 2011 | 101 | 2011 |
| Exploration of GPGPU register file architecture using domain-wall-shift-write based racetrack memory M Mao, W Wen, Y Zhang, Y Chen, H Li Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014 | 90 | 2014 |
| STT-RAM cell optimization considering MTJ and CMOS variations Y Zhang, X Wang, H Li, Y Chen IEEE Transactions on Magnetics 47 (10), 2962-2965, 2011 | 64 | 2011 |
| On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations Y Chen, WF Wong, H Li, CK Koh, Y Zhang, W Wen ACM Journal on Emerging Technologies in Computing Systems (JETC) 9 (2), 1-22, 2013 | 63 | 2013 |
| Read performance: The newest barrier in scaled STT-RAM Y Zhang, Y Li, Z Sun, H Li, Y Chen, AK Jones IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (6 …, 2014 | 55 | 2014 |
| State-restrict MLC STT-RAM designs for high-reliable high-performance memory system W Wen, Y Zhang, M Mao, Y Chen Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014 | 53 | 2014 |
| The prospect of STT-RAM scaling from readability perspective Y Zhang, W Wen, Y Chen IEEE Transactions on Magnetics 48 (11), 3035-3038, 2012 | 51 | 2012 |
| Performance, power, and reliability tradeoffs of STT-RAM cell subject to architecture-level requirement H Li, X Wang, ZL Ong, WF Wong, Y Zhang, P Wang, Y Chen IEEE Transactions on Magnetics 47 (10), 2356-2359, 2011 | 48 | 2011 |
| Radiation-induced soft error analysis of STT-MRAM: A device to circuit approach J Yang, P Wang, Y Zhang, Y Cheng, W Zhao, Y Chen, HH Li IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015 | 41 | 2015 |
| PS3-RAM: A fast portable and scalable statistical STT-RAM reliability analysis method W Wen, Y Zhang, Y Chen, Y Wang, Y Xie Proceedings of the 49th Annual Design Automation Conference, 1191-1196, 2012 | 38 | 2012 |
| Giant spin hall effect (GSHE) logic design for low power application Y Zhang, B Yan, W Wu, H Li, Y Chen 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015 | 35 | 2015 |
| Improving energy efficiency of write-asymmetric memories by log style write G Sun, Y Zhang, Y Wang, Y Chen Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012 | 32 | 2012 |
| Adams: asymmetric differential stt-ram cell structure for reliable and high-performance applications Y Zhang, I Bayram, Y Wang, H Li, Y Chen 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 9-16, 2013 | 28 | 2013 |
| A novel self-reference technique for STT-RAM read and write reliability enhancement E Eken, Y Zhang, W Wen, R Joshi, H Li, Y Chen IEEE Transactions on Magnetics 50 (11), 1-4, 2014 | 24 | 2014 |
| An energy-efficient GPGPU register file architecture using racetrack memory M Mao, W Wen, Y Zhang, Y Chen, H Li IEEE Transactions on Computers 66 (9), 1478-1490, 2017 | 23 | 2017 |
| C1C: A configurable, compiler-guided STT-RAM L1 cache Y Li, Y Zhang, H Li, Y Chen, AK Jones ACM Transactions on Architecture and Code Optimization (TACO) 10 (4), 1-22, 2013 | 23 | 2013 |
| A novel PUF based on cell error rate distribution of STT-RAM X Zhang, G Sun, Y Zhang, Y Chen, H Li, W Wen, J Di 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 342-347, 2016 | 21 | 2016 |
Yiran ChenJohn Cocke Distinguished Professor of Electrical and Computer Engineering, Duke UniversityDirección de correo verificada de duke.edu