| The ISPD2005 placement contest and benchmark suite GJ Nam, CJ Alpert, P Villarrubia, B Winter, M Yildiz Proceedings of the 2005 international symposium on Physical design, 216-220, 2005 | 189 | 2005 |
| Fractional cut: Improved recursive bisection placement A Agnihotri, MC Yildiz, A Khatkhate, A Mathur, S Ono, PH Madden ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003 | 134 | 2003 |
| Recursive bisection based mixed block placement A Khatkhate, C Li, AR Agnihotri, MC Yildiz, S Ono, CK Koh, PH Madden Proceedings of the 2004 international symposium on Physical design, 84-89, 2004 | 125 | 2004 |
| Benchmarking for large-scale placement and beyond SN Adya, MC Yildiz, IL Markov, PG Villarrubia, PN Parakh, PH Madden Proceedings of the 2003 international symposium on Physical design, 95-103, 2003 | 101 | 2003 |
| Techniques for fast physical synthesis CJ Alpert, SK Karandikar, Z Li, GJ Nam, ST Quay, H Ren, CN Sze, ... Proceedings of the IEEE 95 (3), 573-599, 2007 | 86 | 2007 |
| Global objectives for standard cell placement MC Yildiz, PH Madden Proceedings of the 11th Great Lakes symposium on VLSI, 68-72, 2001 | 73 | 2001 |
| The ISPD global routing benchmark suite GJ Nam, C Sze, M Yildiz Proceedings of the 2008 international symposium on Physical design, 156-159, 2008 | 58 | 2008 |
| Mixed block placement via fractional cut recursive bisection AR Agnihotri, S Ono, C Li, MC Yildiz, A Khatkhate, CK Koh, PH Madden IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2005 | 53 | 2005 |
| Preferred direction Steiner trees MC Yildiz, PH Madden Proceedings of the 11th Great Lakes symposium on VLSI, 56-61, 2001 | 41 | 2001 |
| ISPD placement contest updates and ISPD 2007 global routing contest GJ Nam, M Yildiz, DZ Pan, PH Madden Proceedings of the 2007 international symposium on Physical design, 167-167, 2007 | 34 | 2007 |
| Stability metrics for placement to quantify the stability of placement algorithms CJ Alpert, GJ Nam, PG Villarrubia, MC Yildiz US Patent 7,073,144, 2006 | 20 | 2006 |
| Placement stability metrics CJ Alpert, GJ Nam, P Villarribua, MC Yildiz Proceedings of the 2005 Asia and South Pacific Design Automation Conference …, 2005 | 15 | 2005 |
| Fast electrical correction using resizing and buffering SK Karandikar, CJ Alpert, MC Yildiz, P Villarrubia, S Quay, T Mahmud 2007 Asia and South Pacific Design Automation Conference, 553-558, 2007 | 9 | 2007 |
| Method and system for providing immunity to computers M Yildiz US Patent 8,271,834, 2012 | 7 | 2012 |
| System and method for routing in an integrated circuit design WK Chow, M Yildiz, Z Li US Patent 10,755,024, 2020 | 5 | 2020 |
| Routing congestion based on layer-assigned net and placement blockage G Posser, MC Yildiz, WH Liu, C Wing-Kai, Z Li, D Liu US Patent 10,997,352, 2021 | 4 | 2021 |
| Circuit design routing using multi-panel track assignment YX Ding, MC Yildiz US Patent 10,706,201, 2020 | 4 | 2020 |
| Routing framework to resolve single-entry constraint violations for integrated circuit designs G Posser, WH Liu, C Wing-Kai, MC Yildiz, Z Li US Patent 10,460,066, 2019 | 4 | 2019 |
| System and Method of Eliminating Electrical Violations AK Karandikar, CJ Alpert, MC Yildiz, ST Quay, T Mahmud, PG Villarrubia US Patent App. 11/422,174, 2007 | 4 | 2007 |
| Routing congestion based on via spacing and pin density G Posser, C Wing-Kai, MC Yildiz, Z Li US Patent 10,885,257, 2021 | 3 | 2021 |
