A 3.3-mW 25.2-to-29.4-GHz current-reuse VCO using a single-turn multi-tap inductor and differential-only switched-capacitor arrays with a 187.6-dBc/Hz FOM Y Huang, Y Chen, H Guo, PI Mak, RP Martins
IEEE Transactions on Circuits and Systems I: Regular Papers 67 (11), 3704-3717, 2020
54 2020 Total ionizing dose response and annealing behavior of bulk nFinFETs with ON-state bias irradiation L Yang, Q Zhang, Y Huang, Z Zheng, B Li, B Li, X Zhang, H Zhu, H Yin, ...
IEEE Transactions on Nuclear Science 65 (8), 1503-1510, 2018
31 2018 A 2 0.98-to-1.5 mW Nonself-Oscillation-Mode Frequency Divider-by-2 Achieving a Single-Band Untuned Locking Range of 166.6% (4–44 GHz) Y Chen, Z Yang, X Zhao, Y Huang, PI Mak, RP Martins
IEEE Solid-State Circuits Letters 2 (5), 37-40, 2019
25 2019 A 3.36-GHz locking-tuned type-I sampling PLL with− 78.6-dBc reference spur merging single-path reference-feedthrough-suppression and narrow-pulse-shielding techniques Y Huang, Y Chen, H Jiao, PI Mak, RP Martins
IEEE Transactions on Circuits and Systems II: Express Briefs 68 (9), 3093-3097, 2021
20 2021 A 3.52-GHz harmonic-rich-shaping VCO with noise suppression and circulation, achieving-151-dBc/Hz phase noise at 10-MHz offset Y Huang, Y Chen, PI Mak, RP Martins
2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2021
20 2021 Process variation dependence of total ionizing dose effects in bulk nFinFETs B Li, YB Huang, L Yang, QZ Zhang, ZS Zheng, BH Li, HP Zhu, JH Bu, ...
Microelectronics Reliability 88, 946-951, 2018
14 2018 A 3.78-GHz Type-I Sampling PLL With a Fully Passive KPD -Doubled Primary–Secondary S-PD Measuring 39.6-fsRMS Jitter, −260.2-dB FOM, and −70.96–dBc … Y Huang, Y Chen, B Zhao, PI Mak, RP Martins
IEEE Transactions on Circuits and Systems I: Regular Papers 70 (4), 1463-1475, 2023
10 2023 8.4 An 83.3-to-104.7 GHz Harmonic-Extraction VCO Incorporating Multi-Resonance, Multi-Core, and Multi-Mode (3M) Techniques Achieving-124dBc/Hz Absolute PN and 190.7 dBc/Hz … H Guo, Y Chen, Y Huang, PI Mak, RP Martins
2023 IEEE International Solid-State Circuits Conference (ISSCC), 152-154, 2023
8 2023 A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fsRMS Jitter, −258.7-dB FOM, and −75.17-dBc Reference Spur Y Huang, Y Chen, B Zhao, PI Mak, RP Martins
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 31 (2), 188-198, 2022
8 2022 Constant voltage stress characterization of nFinFET transistor during total ionizing dose experiment B Li, Y Huang, J Wu, Q Zhang, L Yang, F Wan, J Luo, Z Han, H Yin
Microelectronics Reliability 88, 969-973, 2018
5 2018 A 9.97-GHz 190.6-dBc/Hz FOM CMOS VCO Featuring Nested Common-Mode Resonator and Intrinsic Differential 2nd -Harmonic Output Y Huang, Y Chen, C Yang, PI Mak, RP Martins
2023 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2023
3 2023 A 28-nm 368-fJ/Cycle, 0.43%/V Supply-Sensitivity, FLL-Based RC Oscillator Featuring Positive-TC-Only Resistors and ΔΣM-Based Trimming Y Huang, Y Chen, K Yang, P Crovetti, PI Mak, RP Martins
IEEE Transactions on Circuits and Systems II: Express Briefs 70 (11), 3950-3954, 2023
3 2023 Universal stability criterion for type-i sampling phase-locked loops Y Huang, Y Chen, PI Mak, RP Martins
IEEE Transactions on Circuits and Systems II: Express Briefs 70 (4), 1351-1355, 2022
3 2022 A 6-GHz 78-fs H Ren, Z Yang, Y Huang, C Feng, T Chen, X Zhang, X Meng, W Yan, ...
IEEE Microwave and Wireless Technology Letters, 2024
2 2024 7.4 A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and -74.2dBc Reference Spur Y Huang, Y Chen, Z Yang, RP Martins, PI Mak
2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 130-132, 2024
1 2024 A 5.99-GHz VCO With Wideband-Differential-Mode Second Harmonic Resonance Achieving C Yang, Y Chen, Y Huang, RP Martins, PI Mak
IEEE Microwave and Wireless Technology Letters, 2024
2024 A Type-II Reference-Sampling PLL with Non-Uniform Octuple-Sampling Phase Detector Achieving 55-fs JitterRMS , –91.9-dBc Reference Spur and –259-dB Jitter … H Ren, Y Huang, Z Yang, T Chen, X Meng, W Yan, W Zhang, Z Li, T Iizuka, ...
2024 IEEE European Solid-State Electronics Research Conference (ESSERC), 113-116, 2024
2024 A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter, and -76.5-dBc Reference Spur T Chen, H Ren, Z Yang, Y Huang, X Meng, W Yan, W Zhang, X Zheng, ...
2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2024
2024 
Pui-In Mak (Elvis)Professor at University of Macau | IEEE Fellow | IET Fellow | RSC FellowDirección de correo verificada de umac.mo