| A 3-GHz 70-Mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply K Zhang, U Bhattacharya, Z Chen, F Hamzaoglu, D Murray, N Vallepalli, ... IEEE Journal of Solid-State Circuits 41 (1), 146-151, 2005 | 462 | 2005 |
| SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction K Zhang, U Bhattacharya, Z Chen, F Hamzaoglu, D Murray, N Vallepalli, ... IEEE Journal of Solid-State Circuits 40 (4), 895-901, 2005 | 305 | 2005 |
| A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications Q Dong, ME Sinangil, B Erbagci, D Sun, WS Khwa, HJ Liao, Y Wang, ... 2020 IEEE International Solid-State Circuits Conference, pp.132-133, 2020 | 292 | 2020 |
| An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications TYJC Y-D. Chih, P-H. Lee, H. Fujiwara, Y-C. Shih, C-F. Lee, R. Naous, Y-L ... 2021 IEEE International Solid-State Circuits Conference, 2021 | 251* | 2021 |
| SRAM and logic transistors with variable height multi-gate transistor architecture S Datta, BS Doyle, JT Kavalieros, Y Wang US Patent App. 11/648,521, 2008 | 248 | 2008 |
| A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry E Karl, Y Wang, YG Ng, Z Guo, F Hamzaoglu, U Bhattacharya, K Zhang, ... 2012 IEEE International Solid-State Circuits Conference, 230-232, 2012 | 232 | 2012 |
| Erratic fluctuations of SRAM cache Vmin at the 90nm process technology node M Agostinelli, J Hicks, J Xu, B Woolery, K Mistry, K Zhang, S Jacobs, ... IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest …, 2005 | 149 | 2005 |
| A 1.1 GHz 12 μA/Mb-leakage SRAM design in 65 nm ultra-low-power CMOS technology with integrated leakage reduction for mobile applications Y Wang, HJ Ahn, U Bhattacharya, C Zhanping, T Coan, F Hamzaoglu, ... IEEE Journal of Solid-State Circuits 43 (1), 172-179, 2008 | 138 | 2008 |
| A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous … H Fujiwara, H Mori, WC Zhao, MC Chuang, R Naous, CK Chuang, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 137 | 2022 |
| A 7nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS JC M. E. Sinangil, B. Erbagci, D. Sun, W-S. Khwa, H-J. Liao, Y. Wang IEEE Journal of Solid State Circuits, 2021 | 137* | 2021 |
| SRAM design on 65nm CMOS technology with integrated leakage reduction scheme K Zhang, U Bhattacharya, Z Chen, F Hamzaoglu, D Murray, N Vallepalli, ... 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No …, 2004 | 104 | 2004 |
| A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management Y Wang, U Bhattacharya, F Hamzaoglu, P Kolar, Y Ng, L Wei, Y Zhang, ... 2009 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2009 | 79 | 2009 |
| A 4.6 GHz 162 Mb SRAM design in 22 nm tri-gate CMOS technology with integrated read and write assist circuitry E Karl, Y Wang, YG Ng, Z Guo, F Hamzaoglu, M Meterelliyoz, J Keane, ... IEEE Journal of Solid-State Circuits 48 (1), 150-158, 2012 | 76 | 2012 |
| 13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology F Hamzaoglu, U Arslan, N Bisnik, S Ghosh, MB Lal, N Lindert, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 69 | 2014 |
| A 153Mb-SRAM design with dynamic stability enhancement and leakage reduction in 45nm high-κ metal-gate CMOS technology F Hamzaoglu, K Zhang, Y Wang, HJ Ahn, U Bhattacharya, Z Chen, YG Ng, ... 2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008 | 69 | 2008 |
| A 65nm ultra low power logic platform technology using uni-axial strained silicon transistors CH Jan, P Bai, J Choi, G Curello, S Jacobs, J Jeong, K Johnson, D Jones, ... IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., 60-63, 2005 | 68 | 2005 |
| A 3.8 GHz 153 Mb SRAM design with dynamic stability enhancement and leakage reduction in 45 nm high-k metal gate CMOS technology F Hamzaoglu, K Zhang, Y Wang, HJ Ahn, U Bhattacharya, Z Chen, YG Ng, ... IEEE Journal of Solid-State Circuits 44 (1), 148-154, 2008 | 65 | 2008 |
| A 32nm High-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation H Nho, P Kolar, F Hamzaoglu, Y Wang, E Karl, YG Ng, U Bhattacharya, ... 2010 IEEE International Solid-State Circuits Conference-(ISSCC), 346-347, 2010 | 63 | 2010 |
| A 4.0 GHz 291 Mb voltage-scalable SRAM design in a 32 nm high-k+ metal-gate CMOS technology with integrated power management Y Wang, U Bhattacharya, F Hamzaoglu, P Kolar, YG Ng, L Wei, Y Zhang, ... IEEE Journal of Solid-State Circuits 45 (1), 103-110, 2009 | 59 | 2009 |
| A 45nm low power system-on-chip technology with dual gate (logic and I/O) high-k/metal gate strained silicon transistors CH Jan, P Bai, S Biswas, M Buehler, ZP Chen, G Curello, S Gannavaram, ... 2008 IEEE International Electron Devices Meeting, 1-4, 2008 | 56 | 2008 |
Fatih HamzaogluFellow, Intel CorporationVerified email at intel.com
