| FinFET SRAM cell using low mobility plane for cell stability and method for forming DM Fried, RW Mann, KP Muller, EJ Nowak US Patent 7,087,477, 2006 | 361 | 2006 |
| Fluctuation limits & scaling opportunities for CMOS SRAM cells A Bhavnagarwala, S Kosonocky, C Radens, K Stawiasz, R Mann, Q Ye, ... IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest …, 2005 | 214 | 2005 |
| SRAM cell design for stability methodology C Wann, R Wong, DJ Frank, R Mann, SB Ko, P Croce, D Lea, D Hoyniak, ... IEEE VLSI-TSA International Symposium on VLSI Technology, 2005.(VLSI-TSA …, 2005 | 180 | 2005 |
| Finfet SRAM cell using low mobility plane for cell stability and method for forming DM Fried, RW Mann, KP Muller, EJ Nowak US Patent 6,967,351, 2005 | 154 | 2005 |
| Reduction of the C54–TiSi2 phase transformation temperature using refractory metal ion implantation RW Mann, GL Miles, TA Knotts, DW Rakowski, LA Clevenger, JME Harper, ... Applied physics letters 67 (25), 3729-3731, 1995 | 143 | 1995 |
| Lateral ion implant straggle and mask proximity effect TB Hook, J Brown, P Cottrell, E Adler, D Hoyniak, J Johnson, R Mann IEEE Transactions on Electron Devices 50 (9), 1946-1951, 2003 | 134 | 2003 |
| Silicides and local interconnections for high-performance VLSI applications RW Mann, LA Clevenger, PD Agnello, FR White IBM Journal of Research and Development 39 (4), 403-417, 1995 | 131 | 1995 |
| Semiconductor integrated test structures for electron beam inspection of semiconductor wafers MC Sun, S Jansen, R Mann, OD Patterson US Patent 7,679,083, 2010 | 124 | 2010 |
| High performance and low power transistors integrated in 65nm bulk CMOS technology Z Luo, A Steegen, M Eller, R Mann, C Baiocco, P Nguyen, L Kim, ... IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004 | 106 | 2004 |
| Enchanced multi-threshold (mtcmos) circuits using variable well bias SV Kosonocky, M Immediato, P Cottrell, T Hook, R Mann, J Brown Proceedings of the 2001 international symposium on Low power electronics and …, 2001 | 98 | 2001 |
| The C49 to C54 phase transformation in TiSi2 thin films RW Mann, LA Clevenger Journal of The Electrochemical Society 141 (5), 1347, 1994 | 98 | 1994 |
| Semiconductor structure incorporating thin film transistors with undoped cap oxide layers BA Chen, SB Kulkarni, JB Lasky, RW Mann, EJ Nowak, WA Rausch, ... US Patent 5,675,185, 1997 | 96 | 1997 |
| Sub-threshold circuit design with shrinking CMOS devices BH Calhoun, S Khanna, R Mann, J Wang 2009 IEEE International Symposium on Circuits and Systems, 2541-2544, 2009 | 89 | 2009 |
| Kinetic analysis of C49‐TiSi2 and C54‐TiSi2 formation at rapid thermal annealing rates LA Clevenger, JME Harper, C Cabral Jr, C Nobili, G Ottaviani, R Mann Journal of applied physics 72 (10), 4978-4980, 1992 | 87 | 1992 |
| Low temperature formation of using titanium alloys C Cabral Jr, LA Clevenger, JME Harper, FM d’Heurle, RA Roy, C Lavoie, ... Applied physics letters 71 (24), 3531-3533, 1997 | 84 | 1997 |
| Impact of circuit assist methods on margin and performance in 6T SRAM RW Mann, J Wang, S Nalam, S Khanna, G Braceras, H Pilo, BH Calhoun Solid-State Electronics 54 (11), 1398-1407, 2010 | 74 | 2010 |
| Borderless contact to diffusion with respect to gate conductor and methods for fabricating JA Bruce, JD Chapple-Sokol, CW Koburger III, MJ Lercel, RW Mann, ... US Patent 6,498,096, 2002 | 68 | 2002 |
| Grounded body SOI SRAM cell F Assaderaghi, A Bryant, PE Cottrell, RJ Gauthier Jr, RW Mann, EJ Nowak, ... US Patent 6,646,305, 2003 | 66 | 2003 |
| Ultralow-power SRAM technology RW Mann, WW Abadeer, MJ Breitwisch, O Bula, JS Brown, BC Colwill, ... IBM Journal of Research and Development 47 (5.6), 553-566, 2003 | 65 | 2003 |
| 65nm CMOS technology for low power applications A Steegen, R Mo, R Mann, MC Sun, M Eller, G Leake, D Vietzke, A Tilke, ... IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., 64-67, 2005 | 64 | 2005 |
Terence HookIBMVerified email at us.ibm.com