| A scaling roadmap and performance evaluation of in-plane and perpendicular MTJ based STT-MRAMs for high-density cache memory KC Chun, H Zhao, JD Harms, TH Kim, JP Wang, CH Kim IEEE journal of solid-state circuits 48 (2), 598-610, 2012 | 426 | 2012 |
| A 3T gain cell embedded DRAM utilizing preferential boosting for high density and low power on-die caches KC Chun, P Jain, JH Lee, CH Kim IEEE Journal of Solid-State Circuits 46 (6), 1495-1505, 2011 | 144 | 2011 |
| A 667 MHz logic-compatible embedded DRAM featuring an asymmetric 2T gain cell for high speed on-die caches KC Chun, P Jain, TH Kim, CH Kim IEEE Journal of Solid-State Circuits 47 (2), 547-559, 2011 | 124 | 2011 |
| A 2T1C embedded DRAM macro with no boosted supplies featuring a 7T SRAM based repair and a cell storage monitor KC Chun, W Zhang, P Jain, CH Kim IEEE journal of solid-state circuits 47 (10), 2517-2526, 2012 | 64 | 2012 |
| 22.1 A 1.1 V 16GB 640GB/s HBM2E DRAM with a data-bus window-extension technique and a synergetic on-die ECC scheme CS Oh, KC Chun, YY Byun, YK Kim, SY Kim, Y Ryu, J Park, S Kim, S Cha, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 330-332, 2020 | 61 | 2020 |
| A sub-0.9 V logic-compatible embedded DRAM with boosted 3T gain cell, regulated bit-line write scheme and PVT-tracking read reference bias KC Chun, P Jain, JH Lee, CH Kim 2009 Symposium on VLSI Circuits, 134-135, 2009 | 56 | 2009 |
| A logic-compatible embedded flash memory for zero-standby power system-on-chips featuring a multi-story high voltage switch and a selective refresh scheme SH Song, KC Chun, CH Kim IEEE Journal of Solid-state circuits 48 (5), 1302-1314, 2013 | 45 | 2013 |
| A 1.8-V 128-Mb mobile DRAM with double boosting pump, hybrid current sense amplifier, and dual-referenced adjustment scheme for temperature sensor JY Sim, H Yoon, KC Chun, HS Lee, SP Hong, KC Lee, JH Yoo, DI Seo, ... IEEE Journal of Solid-State Circuits 38 (4), 631-640, 2003 | 38 | 2003 |
| A 1.1 V, 667MHz random cycle, asymmetric 2T gain cell embedded DRAM with a 99.9 percentile retention time of 110µsec KC Chun, P Jain, TH Kim, CH Kim 2010 Symposium on VLSI Circuits, 191-192, 2010 | 34 | 2010 |
| A 16-GB 640-GB/s HBM2E DRAM with a data-bus window extension technique and a synergetic on-die ECC scheme KC Chun, YK Kim, Y Ryu, J Park, CS Oh, YY Byun, SY Kim, DH Shin, ... IEEE Journal of Solid-State Circuits 56 (1), 199-211, 2020 | 33 | 2020 |
| Two-dimensional nozzle arrangement in a monolithic inkjet printhead for high-resolution and high-speed printing JD Lee, CS Lee, KC Chun, CH Han International Electron Devices Meeting 1999. Technical Digest (Cat. No …, 1999 | 29 | 1999 |
| Semiconductor memory devices having negatively biased sub word line scheme and methods of driving the same KC Chun US Patent 7,248,535, 2007 | 28 | 2007 |
| Memory system with reduced pin count BG Park, KC Chun, JH Choi, HS Jang, WS Jeong US Patent App. 10/865,887, 2004 | 28 | 2004 |
| Internal voltage source generator in semiconductor memory device SJ Rhee, JY Sim, S Hong, KC Chun US Patent 6,774,712, 2004 | 28 | 2004 |
| A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm … KC Chun, YG Chu, JS Heo, TS Kim, S Kim, HK Yang, MJ Kim, CK Lee, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 206-208, 2018 | 24 | 2018 |
| Power-on reset circuit, semiconductor integrated circuit device including the same and method for generating a power-on reset signal KC Chun, JY Sim US Patent 7,091,758, 2006 | 23 | 2006 |
| A 700MHz 2T1C embedded DRAM macro in a generic logic process with no boosted supplies KC Chun, W Zhang, P Jain, CH Kim 2011 IEEE International Solid-State Circuits Conference, 506-507, 2011 | 22 | 2011 |
| A write-back-free 2T1D embedded DRAM with local voltage sensing and a dual-row-access low power mode W Zhang, KC Chun, CH Kim IEEE Transactions on Circuits and Systems I: Regular Papers 60 (8), 2030-2038, 2013 | 20 | 2013 |
| Semiconductor memory device and body bias method thereof K Chun US Patent 9,251,866, 2016 | 18 | 2016 |
| A bit-by-bit re-writable eflash in a generic 65 nm logic process for moderate-density nonvolatile memory applications SH Song, KC Chun, CH Kim IEEE Journal of solid-state circuits 49 (8), 1861-1871, 2014 | 18 | 2014 |
Chris H. KimMcknight Presidential Endowed Chair, University of MinnesotaVerified email at umn.edu