| Detecting Trojans Through Leakage Current Analysis Using Multiple Supply Pads J Aarestad, D Acharyya, R Rad, J Plusquellic IEEE Transactions on information forensics and security 5 (4), 893-904, 2010 | 209 | 2010 |
| A 5.3 GHz 8T-SRAM with operation down to 0.41 V in 65nm CMOS L Chang, Y Nakamura, RK Montoye, J Sawada, AK Martin, K Kinoshita, ... 2007 IEEE Symposium on VLSI Circuits, 252-253, 2007 | 208 | 2007 |
| A physical unclonable function defined using power distribution system equivalent resistance variations R Helinski, D Acharyya, J Plusquellic Proceedings of the 46th Annual Design Automation Conference, 676-681, 2009 | 160 | 2009 |
| Rigorous extraction of process variations for 65-nm CMOS design W Zhao, F Liu, K Agarwal, D Acharyya, SR Nassif, KJ Nowka, Y Cao IEEE Transactions on Semiconductor Manufacturing 22 (1), 196-203, 2009 | 145 | 2009 |
| A test structure for characterizing local device mismatches K Agarwal, F Liu, C McDowell, S Nassif, K Nowka, M Palmer, D Acharyya, ... 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers., 67-68, 2006 | 138 | 2006 |
| HELP: A hardware-embedded delay PUF J Aarestad, P Ortiz, D Acharyya, J Plusquellic IEEE Design & Test 30 (2), 17-25, 2013 | 56 | 2013 |
| System and methods for generating unclonable security keys in integrated circuits J Plusquellic, DJ Acharyya, RL Helinski US Patent 8,610,454, 2013 | 45 | 2013 |
| Impedance profile of a commercial power grid and test system D Acharyya, J Plusquellic International Test Conference, 2003. Proceedings. ITC 2003., 709-709, 2003 | 26 | 2003 |
| A transmission gate physical unclonable function and on-chip voltage-to-digital conversion technique R Chakraborty, C Lamech, D Acharyya, J Plusquellic Proceedings of the 50th Annual Design Automation Conference, 1-10, 2013 | 21 | 2013 |
| Hardware results demonstrating defect detection using power supply signal measurements D Acharyya, J Plusquellic 23rd IEEE VLSI Test Symposium (VTS'05), 433-438, 2005 | 19 | 2005 |
| Error-tolerant bit generation techniques for use with a hardware-embedded path delay PUF J Aarestad, J Plusquellic, D Acharyya 2013 IEEE International Symposium on Hardware-Oriented Security and Trust …, 2013 | 18 | 2013 |
| On-chip jitter and oscilloscope circuits using an asynchronous sample clock JD Schaub, FH Gebara, TY Nguyen, I Vo, J Pena, DJ Acharyya ESSCIRC 2008-34th European Solid-State Circuits Conference, 126-129, 2008 | 18 | 2008 |
| Method and circuit for measuring operating and leakage current of individual blocks within an array of test circuit blocks DJ Acharyya, SR Nassif, RM Rao US Patent 7,550,987, 2009 | 16 | 2009 |
| Quality metric evaluation of a physical unclonable function derived from an IC's power distribution system R Helinski, D Acharyya, J Plusquellic Proceedings of the 47th Design Automation Conference, 240-243, 2010 | 13 | 2010 |
| Defect diagnosis using a current ratio based quiescent signal analysis model for commercial power grids C Patel, E Staroswiecki, S Pawar, D Acharyya, J Plusquellic Journal of Electronic Testing 19, 611-623, 2003 | 13 | 2003 |
| Quiescent-signal analysis: a multiple supply pad IDDQ method J Plusquellic, D Acharyya, A Singh, M Tehranipoor, C Patel IEEE Design & Test of Computers 23 (4), 278-293, 2006 | 12 | 2006 |
| Calibrating power supply signal measurements for process and probe card variations D Acharyya, J Plusquellic Proceedings. 2004 IEEE International Workshop on Current and Defect Based …, 2004 | 12 | 2004 |
| Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effect J Aarestad, C Lamech, J Plusquellic, D Acharyya, K Agarwal Proceedings of the 48th Design Automation Conference, 534-539, 2011 | 10 | 2011 |
| Hardware results demonstrating defect localization using power supply signal measurements D Acharyya, J Plusquellic International Symposium for Testing and Failure Analysis 30873, 58-66, 2004 | 10 | 2004 |
| Diagnosis using quiescent signal analysis on a commercial power grid C Patel, E Staroswiecki, S Pawar, D Acharyya, J Plusquellic International Symposium for Testing and Failure Analysis 30774, 713-722, 2002 | 10 | 2002 |
