| Low temperature implementation of dopant-segregated band-edge metallic S/D junctions in thin-body SOI p-MOSFETs G Larrieu, E Dubois, R Valentin, N Breil, F Danneville, G Dambrine, ... 2007 IEEE International Electron Devices Meeting, 147-150, 2007 | 300 | 2007 |
| Arsenic-segregated rare-earth silicide junctions: reduction of Schottky barrier and integration in metallic n-MOSFETs on SOI G Larrieu, DA Yarekha, E Dubois, N Breil, O Faynot IEEE Electron Device Letters 30 (12), 1266-1268, 2009 | 289 | 2009 |
| Gold-free growth of GaAs nanowires on silicon: arrays and polytypism S Plissard, KA Dick, G Larrieu, S Godey, A Addad, X Wallart, P Caroff Nanotechnology 21 (38), 385602, 2010 | 215 | 2010 |
| High yield of self-catalyzed GaAs nanowire arrays grown on silicon via gallium droplet positioning S Plissard, G Larrieu, X Wallart, P Caroff Nanotechnology 22 (27), 275602, 2011 | 213 | 2011 |
| Vertical nanowire array-based field effect transistors for ultimate scaling G Larrieu, XL Han Nanoscale 5 (6), 2437-2441, 2013 | 210 | 2013 |
| Evolutionary multi-objective optimization of colour pixels based on dielectric nanoantennas PR Wiecha, A Arbouet, C Girard, A Lecestre, G Larrieu, V Paillard Nature nanotechnology 12 (2), 163-169, 2017 | 143 | 2017 |
| Vertical silicon nanowire field effect transistors with nanoscale gate-all-around Y Guerfi, G Larrieu Nanoscale research letters 11, 1-7, 2016 | 139 | 2016 |
| Measurement of low Schottky barrier heights applied to metallic source/drain metal–oxide–semiconductor field effect transistors E Dubois, G Larrieu Journal of applied physics 96 (1), 729-737, 2004 | 139 | 2004 |
| Formation of platinum-based silicide contacts: Kinetics, stoichiometry, and current drive capabilities G Larrieu, E Dubois, X Wallart, X Baie, J Katcki Journal of Applied Physics 94 (12), 7801-7810, 2003 | 122 | 2003 |
| Pushing the limits of optical information storage using deep learning PR Wiecha, A Lecestre, N Mallet, G Larrieu Nature nanotechnology 14 (3), 237-244, 2019 | 120 | 2019 |
| Large-scale assembly of single nanowires through capillary-assisted dielectrophoresis. M Collet, S Salomon, NY Klein, F Seichepine, C Vieu, L Nicu, G Larrieu Advanced Materials (Deerfield Beach, Fla.) 27 (7), 1268-1273, 2014 | 96 | 2014 |
| Strongly directional scattering from dielectric nanowires PR Wiecha, A Cuche, A Arbouet, C Girard, G Colas des Francs, ... ACS photonics 4 (8), 2036-2046, 2017 | 83 | 2017 |
| Low Schottky barrier source/drain for advanced MOS architecture: device design and material considerations E Dubois, G Larrieu Solid-State Electronics 46 (7), 997-1004, 2002 | 70 | 2002 |
| Schottky-barrier source/drain MOSFETs on ultrathin SOI body with a tungsten metallic midgap gate G Larrieu, E Dubois IEEE electron device letters 25 (12), 801-803, 2004 | 65 | 2004 |
| Process for fabricating a field-effect transistor device implemented on a network of vertical nanowires, the resulting transistor device, an electronic device comprising such … G Larrieu US Patent 9,379,238, 2016 | 54 | 2016 |
| Very low Schottky barrier to n-type silicon with PtEr-stack silicide X Tang, J Katcki, E Dubois, N Reckinger, J Ratajczak, G Larrieu, ... Solid-State Electronics 47 (11), 2105-2111, 2003 | 52 | 2003 |
| Integration of PtSi-based Schottky-barrier p-MOSFETs with a midgap tungsten gate G Larrieu, E Dubois IEEE transactions on electron devices 52 (12), 2720-2726, 2005 | 49 | 2005 |
| High resolution HSQ nanopillar arrays with low energy electron beam lithography Y Guerfi, F Carcenac, G Larrieu Microelectronic engineering 110, 173-176, 2013 | 47 | 2013 |
| Electronic transport mechanisms in scaled gate-all-around silicon nanowire transistor arrays N Clément, XL Han, G Larrieu Applied Physics Letters 103 (26), 2013 | 42 | 2013 |
| RF small-signal analysis of Schottky-barrier p-MOSFET R Valentin, E Dubois, JP Raskin, G Larrieu, G Dambrine, TC Lim, N Breil, ... IEEE transactions on electron devices 55 (5), 1192-1202, 2008 | 42 | 2008 |