| Identification of RF harmonic distortion on Si substrates and its reduction using a trap-rich layer DC Kerr, JM Gering, TG McKay, MS Carroll, C Roda Neve, JP Raskin Silicon Monolithic Integrated Circuits in RF Systems, 2008. SiRF 2008. IEEE …, 2008 | 188 | 2008 |
| RF Harmonic Distortion of CPW Lines on HR-Si and Trap-Rich HR-Si Substrates C Roda Neve, JP Raskin IEEE Transactions on Electron Devices 59 (4), 924-932, 2012 | 130 | 2012 |
| RF SOI CMOS technology on commercial trap-rich high resistivity SOI wafer KB Ali, CR Neve, A Gharsallah, JP Raskin 2012 IEEE International SOI Conference (SOI), 1-2, 2012 | 88 | 2012 |
| RF performance of SOI CMOS technology on commercial 200-mm enhanced signal integrity high resistivity SOI substrate KB Ali, CR Neve, A Gharsallah, JP Raskin IEEE Transactions on Electron Devices 61 (3), 722-728, 2014 | 73 | 2014 |
| Ultrawide frequency range crosstalk into standard and trap-rich high resistivity silicon substrates KB Ali, CR Neve, A Gharsallah, JP Raskin IEEE Transactions on Electron Devices 58 (12), 4258-4264, 2011 | 47 | 2011 |
| RF MEMS passives on high-resistivity silicon substrates Y Shim, JP Raskin, CR Neve, M Rais-Zadeh IEEE Microwave and Wireless Components Letters 23 (12), 632-634, 2013 | 45 | 2013 |
| Advanced Si-based substrates for RF passive integration: Comparison between local porous Si layer technology and trap-rich high resistivity Si P Sarafis, E Hourdakis, AG Nassiopoulou, CR Neve, KB Ali, JP Raskin Solid-state electronics 87, 27-33, 2013 | 36 | 2013 |
| Impact of Si substrate resistivity on the non-linear behaviour of RF CPW transmission lines CR Neve, D Lederer, G Pailloncy, DC Kerr, JM Gering, TG McKay, ... 2008 European Microwave Integrated Circuit Conference, 36-39, 2008 | 34 | 2008 |
| Active-lite interposer for 2.5 & 3D integration G Hellings, M Scholz, M Detalle, D Velenis, MP de ten Broeck, CR Neve, ... 2015 Symposium on VLSI Circuits (VLSI Circuits), T222-T223, 2015 | 33 | 2015 |
| PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch P Schuddinck, FM Bufler, Y Xiang, A Farokhnejad, G Mirabelli, ... 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022 | 25 | 2022 |
| RF and linear performance of commercial 200 mm trap-rich HR-SOI wafers for SoC applications C Roda Neve, K Ben Alia, C Malaquin, F Allibert, E Desbonnets, ... Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th …, 2013 | 22* | 2013 |
| Effect of temperature on advanced Si-based substrates performance for RF passive integration CR Neve, KB Ali, P Sarafis, E Hourdakis, AG Nassiopoulou, JP Raskin Microelectronic Engineering 120, 205-209, 2014 | 16 | 2014 |
| Impact of crosstalk into high resistivity silicon substrate on the RF performance of SOI MOSFET KB Ali, C Roda Neve, A Gharsallah, JP Raskin J. Telecommun. Informat. Technol. v3 i4, 93-100, 2010 | 16 | 2010 |
| Spectral characterisation of monolithic modelocked lasers for mm-wave generation and signal processing P Acedo, H Lamela, S Garidel, C Roda, JP Vilcot, G Carpintero, IH White, ... Electronics Letters 42 (16), 928-929, 2006 | 13 | 2006 |
| Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections A Vandooren, N Parihar, J Franco, R Loo, H Arimura, R Rodriguez, ... 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022 | 12 | 2022 |
| The hardware foundation of 6G: The NEW-6G approach EC Strinati, M Peeters, CR Neve, MD Gomony, A Cathelin, MR Boldi, ... 2022 Joint European Conference on Networks and Communications & 6G Summit …, 2022 | 12 | 2022 |
| The effect of a SiO2 interface on RF harmonic distortion in CPW lines on silicon or passivated silicon DC Kerr, JM Gering, T McKay, S Carroll, C Roda Neve, JP Raskin The 8th Topical Meeting on Silicon Monolithic Integrated Circuits in RF …, 2008 | 11 | 2008 |
| High-density and low-leakage novel embedded 3D MIM capacitor on Si interposer CR Neve, M Detalle, P Nolmans, Y Li, J De Vos, G Van der Plas, G Beyer, ... 2016 IEEE International 3D Systems Integration Conference (3DIC), 1-4, 2016 | 10 | 2016 |
| Non-linear characteristics of passive elements on trap-rich high-resistivity Si substrates KB Ali, CR Neve, Y Shim, M Rais-Zadeh, JP Raskin 2014 IEEE 14th Topical Meeting on Silicon Monolithic Integrated Circuits in …, 2014 | 10 | 2014 |
| Photo-induced coplanar waveguide RF switch and optical crosstalk on high-resistivity silicon trap-rich passivated substrate KB Ali, CR Neve, A Gharsallah, JP Raskin IEEE transactions on electron devices 60 (10), 3478-3484, 2013 | 10 | 2013 |
Jean-Pierre RaskinUniversité catholique de Louvain, Engineering School of LouvainVerified email at uclouvain.be