| Accelerating autodock vina with gpus S Tang, R Chen, M Lin, Q Lin, Y Zhu, J Ding, H Hu, M Ling, J Wu Molecules 27 (9), 3041, 2022 | 74 | 2022 |
| An Active Mobile Charging and Data Collection Scheme for Clustered Sensor Networks Kaiyang Liu, Jun Peng, Liang He, Jianping Pan, Shuo Li, Ming Ling, Zhiwu Huang IEEE Transactions on Vehicular Technology, 2019 | 56 | 2019 |
| Vina-GPU 2.0: further accelerating AutoDock Vina and its derivatives with graphics processing units J Ding, S Tang, Z Mei, L Wang, Q Huang, H Hu, M Ling, J Wu Journal of chemical information and modeling 63 (7), 1982-1998, 2023 | 52 | 2023 |
| An embedded implementation of CNN-based hand detection and orientation estimation algorithm L Yang, Z Qi, Z Liu, H Liu, M Ling, L Shi, X Liu Machine Vision and Applications 30, 1071-1082, 2019 | 28 | 2019 |
| A wireless network based on the combination of Zigbee and GPRS S Lin, L Ming 2008 IEEE International Conference on Networking, Sensing and Control, 267-270, 2008 | 24 | 2008 |
| TS cache: A fast cache with timing-speculation mechanism under low supply voltages S Shen, T Shao, X Shang, Y Guo, M Ling, J Yang, L Shi IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (1), 252-262, 2019 | 18 | 2019 |
| An Artificial Neural Network Model of LRU-Cache Misses on Out-of-Order Embedded Processors K Ji, M Ling, Y Zhang, L Shi Microprocessors and Microsystems, 66-79, 2017 | 16 | 2017 |
| Effectiveness Analysis of Multiple Initial States Simulated Annealing Algorithm, a Case Study on the Molecular Docking Tool Autodock Vina X Zhou, M Ling, Q Lin, S Tang, J Wu, H Hu Available at SSRN 4120348, 2022 | 15 | 2022 |
| MLoF: machine learning accelerators for the low-cost FPGA platforms R Chen, T Wu, Y Zheng, M Ling Applied sciences 12 (1), 89, 2021 | 12 | 2021 |
| Performance oriented customization of on-chip memory capacity H PU, M LING Journal of Applied Sciences, 364, 2005 | 12 | 2005 |
| Vina-FPGA: A hardware-accelerated molecular docking tool with fixed-point quantization and low-level parallelism M Ling, Q Lin, R Chen, H Qi, M Lin, Y Zhu, J Wu IEEE Transactions on Very Large Scale Integration (VLSI) Systems 31 (4), 484-497, 2022 | 11 | 2022 |
| AFEC: An analytical framework for evaluating cache performance in out-of-order processors K Ji, M Ling, Q Wang, L Shi, J Pan Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 55-60, 2017 | 11 | 2017 |
| Using the First-level Cache Stack Distance Histograms to Predict Multi-level LRU Cache Misses K Ji, M Ling, L Shi Microprocessors and Microsystems, 55-69, 2017 | 9 | 2017 |
| Lowering the hit latencies of low voltage caches based on the cross-sensing timing speculation SRAM M Ling, X Shang, S Shen, T Shao, J Yang IEEE Access 7, 111649-111661, 2019 | 8 | 2019 |
| Energy-oriented dynamic SPM allocation based on time-slotted cache conflict graph H Wang, Y Zhang, C Mei, M Ling 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010 | 8 | 2010 |
| Implementation of a BIST scheme for ADC test WGW Guanglin, RJR Jin, RAR Ailing, LML Ming 2003 5th International Conference on ASIC Proceedings 2, 1128-1131, 2003 | 8 | 2003 |
| Detecting the phase behavior on cache performance using the reuse distance vectors S Shen, M Ling, Y Zhang, L Shi Journal of Systems Architecture 90, 85-93, 2018 | 7 | 2018 |
| RRS cache: a low voltage cache based on timing speculation SRAM with a reuse-aware cacheline remapping mechanism X Shang, M Ling, S Shen, T Shao, J Yang Proceedings of the International Symposium on Memory Systems, 451-458, 2019 | 6 | 2019 |
| An analytical cache performance evaluation framework for embedded out-of-order processors using software characteristics K Ji, M Ling, L Shi, J Pan ACM Transactions on Embedded Computing Systems (TECS) 17 (4), 1-25, 2018 | 6 | 2018 |
| Extended control flow graph based performance optimization using scratch-pad memory P Hanlai, L Ming, J Jing Design, Automation and Test in Europe, 828-829, 2005 | 6 | 2005 |
Shan ShenTsinghua UniversityVerified email at tsinghua.edu.cn