| High performance eDRAM sense amplifier FH Gebara, JB Kuang, J Sivagnaname, I Vo US Patent 8,164,942, 2012 | 397 | 2012 |
| Method and apparatus for measuring device mismatches KB Agarwal, Y Liu, CT McDowell, SR Nassif, JF Plusquellic, ... US Patent 7,408,372, 2008 | 15 | 2008 |
| Wide limited switch dynamic logic circuit implementations J Sivagnaname, HC Ngo, KJ Nowka, RK Montoye, RB Brown 19th International Conference on VLSI Design held jointly with 5th …, 2006 | 12 | 2006 |
| Wordline-to-bitline output timing ring oscillator circuit for evaluating storage array performance JB Kuang, JC Kao, HC Ngo, KJ Nowka, LT Pang, J Sivagnaname US Patent 7,760,565, 2010 | 11 | 2010 |
| Controlled-load limited switch dynamic logic circuit J Sivagnaname, HC Ngo, KJ Nowka, RK Montoye, RB Brown Sixth international symposium on quality electronic design (isqed'05), 83-87, 2005 | 10 | 2005 |
| Design considerations for PD/SOI SRAM: Impact of gate leakage and threshold voltage variation R Kanj, RV Joshi, J Sivagnaname, JB Kuang, D Acharyya, TY Nguyen, ... IEEE transactions on semiconductor manufacturing 21 (1), 33-40, 2008 | 9 | 2008 |
| Controlled load limited switch dynamic logic circuitry HC Ngo, J Sivagnaname, KJ Nowka, RK Montoye US Patent 7,129,754, 2006 | 9 | 2006 |
| Gate leakage effects on yield and design considerations of PD/SOI SRAM designs R Kanj, R Joshi, J Sivagnaname, JB Kuang, D Acharyya, T Nguyen, ... 8th International Symposium on Quality Electronic Design (ISQED'07), 33-40, 2007 | 7 | 2007 |
| Closed-loop modeling of gate leakage for fast simulators RV Joshi, RN Kanj, Y Liu, SR Nassif, J Sivagnaname US Patent 7,885,798, 2011 | 5 | 2011 |
| Stand-by Current in PD-SOI Pseudo-nMOS circuits Sivagnaname 2003 IEEE International Conference on SOI, 95-96, 2003 | 5 | 2003 |
| Techniques for characterizing performance of transistors in integrated circuit devices SR Nassif, J Sivagnaname US Patent App. 12/061,261, 2009 | 3 | 2009 |
| Active cancellation matrix for process parameter measurements FH Gebara, Y Liu, J Sivagnaname, I Vo US Patent 7,394,276, 2008 | 3 | 2008 |
| Half-select compliant memory cell precharge circuit RV Joshi, R Kanj, J Sivagnaname US Patent 7,751,267, 2010 | 2 | 2010 |
| Method and apparatus for measuring device mismatches KB Agarwal, Y Liu, CT McDowell, SR Nassif, JF Plusquellic, ... US Patent 7,622,942, 2009 | 2 | 2009 |
| Active cancellation matrix for process parameter measurements FH Gebara, Y Liu, J Sivagnaname, I Vo US Patent App. 12/141,899, 2008 | 2 | 2008 |
| Dynamic receiver biasing for inter-chip communication CR Gauthier, J Sivagnaname, RB Brown Proceedings 2001 Conference on Advanced Research in VLSI. ARVLSI 2001, 101-111, 2001 | 2 | 2001 |
| Optical emission spectroscopy investigation of microwave plasmas J Sivagnaname Michigan State University, 1998 | 2 | 1998 |
| Effect of scaling on stand-by current in PD-SOI pseudo-nMOS circuits J Sivagnaname, RB Brown 2003 46th Midwest Symposium on Circuits and Systems 3, 1560-1562, 2003 | 1 | 2003 |
| High-performance SOI pseudo-nMOS circuit design techniques for the deep sub-micron era J Sivagnaname University of Michigan, 2005 | | 2005 |
| EDA Methodologies, Tools, Flows & IP Cores; Interoperability and Reuse T Chen, O Sentieys, A Nunez, CV Kashyap, J Lei, L Melvin, ... | | |
Dharmendra ModhaIBM FellowVerified email at us.ibm.com