| Efficient Overlay architecture based on DSP blocks AK Jain, SA Fahmy, DL Maskell 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom …, 2015 | 81 | 2015 |
| Virtualized execution and management of hardware tasks on a hybrid ARM-FPGA platform AK Jain, KD Pham, J Cui, SA Fahmy, DL Maskell Journal of Signal Processing Systems 77, 61-76, 2014 | 60 | 2014 |
| Microkernel hypervisor for a hybrid ARM-FPGA platform K Dang Pham, AK Jain, J Cui, SA Fahmy, DL Maskell Application-Specific Systems, Architectures and Processors (ASAP), 2013 IEEE …, 2013 | 51 | 2013 |
| Are coarse-grained overlays ready for general purpose application acceleration on fpgas? AK Jain, DL Maskell, SA Fahmy 2016 IEEE 14th Intl Conf on Dependable, Autonomic and Secure Computing, 14th …, 2016 | 48 | 2016 |
| Throughput oriented FPGA overlays using DSP blocks AK Jain, DL Maskell, SA Fahmy 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2016 | 44 | 2016 |
| DeCO: A DSP block based FPGA accelerator overlay with low overhead interconnect AK Jain, X Li, P Singhai, DL Maskell, SA Fahmy IEEE, 2016 | 41 | 2016 |
| Adapting the DySER architecture with DSP blocks as an Overlay for the Xilinx Zynq AK Jain, X Li, SA Fahmy, DL Maskell ACM SIGARCH Computer Architecture News 43 (4), 28-33, 2016 | 33 | 2016 |
| A Domain-Specific Architecture for Accelerating Sparse Matrix Vector Multiplication on FPGAs AK Jain, H Omidian, H Fraisse, M Benipal, L Liu, D Gaitonde 2020 30th International Conference on Field-Programmable Logic and …, 2020 | 29 | 2020 |
| Microscope on memory: MPSoC-enabled computer memory system assessments AK Jain, S Lloyd, M Gokhale Field-Programmable Custom Computing Machines (FCCM), 2018 IEEE Annual …, 2018 | 24 | 2018 |
| Architecture centric coarse-grained FPGA overlays AK Jain | 19 | 2017 |
| An Area-Efficient FPGA Overlay using DSP Block based Time-multiplexed Functional Units X Li, A Jain, D Maskell, SA Fahmy arXiv preprint arXiv:1606.06460, 2016 | 18 | 2016 |
| A time-multiplexed FPGA overlay with linear interconnect X Li, AK Jain, DL Maskell, SA Fahmy 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018 | 14 | 2018 |
| Coarse Grained FPGA Overlay for Rapid Just-In-Time Accelerator Compilation AK Jain, DL Maskell, SA Fahmy IEEE Transactions on Parallel and Distributed Systems 33 (6), 1478-1490, 2021 | 13 | 2021 |
| Performance Assessment of Emerging Memories Through FPGA Emulation AK Jain, S Lloyd, M Gokhale IEEE Micro 39 (1), 8-16, 2018 | 9 | 2018 |
| Resource-Aware Just-in-Time OpenCL Compiler for Coarse-Grained FPGA Overlays AK Jain, DL Maskell, SA Fahmy arXiv preprint arXiv:1705.02730, 2017 | 9 | 2017 |
| Modular and Lean Architecture with Elasticity for Sparse Matrix Vector Multiplication on FPGAs AK Jain, C Ravishankar, H Omidian, S Kumar, M Kulkarni, A Tripathi, ... 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom …, 2023 | 8 | 2023 |
| Sparse Deep Neural Network Acceleration on HBM-Enabled FPGA Platform AK Jain, S Kumar, A Tripathi, D Gaitonde 2021 IEEE High Performance Extreme Computing Conference (HPEC), 1-7, 2021 | 7 | 2021 |
| The Evolution of Domain-Specific Computing for Deep Learning S Neuendorffer, AK Khodamoradi, K Denolf, AK Jain, S Bayliss IEEE Circuits and Systems Magazine 21 (2), 75-96, 2021 | 7 | 2021 |
| High Throughput Accelerator Interface Framework for a Linear Time-Multiplexed FPGA Overlay X Li, K Vipin, DL Maskell, SA Fahmy, AK Jain 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020 | 5 | 2020 |
| 3D STACKED DEVICE HAVING IMPROVED DATA FLOW DD Gaitonde, A Tripathi, A Debnath, DB Moore, MR Kulkarni, AK Jain US Patent App. 18/134,994, 2024 | | 2024 |
Suhaib FahmyAssociate Professor, King Abdullah University of Science and Technology (KAUST)Verified email at kaust.edu.sa