| A three-dimensional quantum simulation of silicon nanowire transistors with the effective-mass approximation J Wang, E Polizzi, M Lundstrom Journal of Applied Physics 96 (4), 2192-2203, 2004 | 454 | 2004 |
| On the validity of the parabolic effective-mass approximation for the IV calculation of silicon nanowire transistors J Wang, A Rahman, A Ghosh, G Klimeck, M Lundstrom IEEE Transactions on Electron Devices 52 (7), 1589-1595, 2005 | 225 | 2005 |
| Does source-to-drain tunneling limit the ultimate scaling of MOSFETs? J Wang, M Lundstrom Digest. International Electron Devices Meeting,, 707-710, 2002 | 206 | 2002 |
| Theoretical investigation of surface roughness scattering in silicon nanowire transistors J Wang, E Polizzi, A Ghosh, S Datta, M Lundstrom Applied Physics Letters 87 (4), 043101, 2005 | 192 | 2005 |
| High performance MOSFET H Zhu, J Wang US Patent 7,704,844, 2010 | 168 | 2010 |
| Ballistic transport in high electron mobility transistors J Wang, M Lundstrom IEEE Transactions on Electron Devices 50 (7), 1604-1609, 2003 | 164 | 2003 |
| Metal gated ultra short MOSFET devices JO Chu, BB Doris, M Ieong, J Wang US Patent 7,348,629, 2008 | 146 | 2008 |
| Artificial Neural Network-Based Compact Modeling Methodology for Advanced Transistors J Wang, YH Kim, J Ryu, C Jeong, W Choi, D Kim IEEE Transactions on Electron Devices 68 (3), 1318-1325, 2021 | 140 | 2021 |
| High performance MOSFET H Zhu, J Wang US Patent 8,299,540, 2012 | 121 | 2012 |
| Electrostatics of nanowire transistors J Guo, J Wang, E Polizzi, S Datta, M Lundstrom IEEE Transactions on Nanotechnology 2 (4), 329-334, 2003 | 121 | 2003 |
| Metal gated ultra short MOSFET devices JO Chu, BB Doris, M Ieong, J Wang US Patent 7,678,638, 2010 | 120 | 2010 |
| Method for metal gated ultra short MOSFET devices JO Chu, BB Doris, M Ieong, J Wang US Patent 7,494,861, 2009 | 119 | 2009 |
| A computational study of ballistic silicon nanowire transistors J Wang, E Polizzi, M Lundstrom International Electron Devices Meeting, 695-698, 2003 | 81 | 2003 |
| Bandstructure and orientation effects in ballistic Si and Ge nanowire FETs J Wang, A Rahman, G Klimeck, M Lundstrom IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., 4 …, 2005 | 76 | 2005 |
| Performance evaluation of ballistic silicon nanowire transistors with atomic-basis dispersion relations J Wang, A Rahman, A Ghosh, G Klimeck, M Lundstrom Applied Physics Letters 86 (9), 093113-093113-3, 2005 | 75 | 2005 |
| Device design and manufacturing issues for 10 nm-scale MOSFETs: a computational study S Hasan, J Wang, M Lundstrom Solid-State Electronics 48 (6), 867-875, 2004 | 68 | 2004 |
| Gate-induced-drain-leakage current in 45-nm CMOS technology X Yuan, JE Park, J Wang, E Zhao, DC Ahlgren, T Hook, J Yuan, ... IEEE Transactions on Device and Materials Reliability 8 (3), 501-508, 2008 | 62 | 2008 |
| Technology scaling and device design for 350 GHz RF performance in a 45nm bulk CMOS process H Li, B Jagannathan, J Wang, TC Su, S Sweeney, JJ Pekarik, Y Shi, ... 2007 IEEE Symposium on VLSI Technology, 56-57, 2007 | 55 | 2007 |
| A general approach for the performance assessment of nanoscale silicon FETs J Wang, PM Solomon, M Lundstrom IEEE transactions on electron devices 51 (9), 1366-1370, 2004 | 41 | 2004 |
| STT-MRAM design technology co-optimization for hardware neural networks N Xu, Y Lu, W Qi, Z Jiang, X Peng, F Chen, J Wang, W Choi, S Yu, DS Kim 2018 IEEE International Electron Devices Meeting (IEDM), 15.3. 1-15.3. 4, 2018 | 37 | 2018 |