| 23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme CK Lee, YJ Eom, JH Park, J Lee, HR Kim, K Kim, Y Choi, HJ Chang, J Kim, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 390-391, 2017 | 36 | 2017 |
| A 1.6 V 1.4 Gbp/s/pin consumer DRAM with self-dynamic voltage scaling technique in 44 nm CMOS technology HW Lee, KH Kim, YK Choi, JH Sohn, NK Park, KW Kim, C Kim, YJ Choi, ... IEEE journal of solid-state circuits 47 (1), 131-140, 2011 | 35 | 2011 |
| Phase control circuit KH Kim US Patent 8,674,733, 2014 | 29 | 2014 |
| 22.2 An 8.5 Gb/s/pin 12Gb-LPDDR5 SDRAM with a hybrid-bank architecture using skew-tolerant, low-power and speed-boosting techniques in a 2nd generation 10nm DRAM process HJ Chi, CK Lee, J Park, JS Heo, J Jung, D Lee, DH Kim, D Park, K Kim, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 382-384, 2020 | 21 | 2020 |
| A 16Gb 9.5 Gb/S/pin LPDDR5X SDRAM with low-power schemes exploiting dynamic voltage-frequency scaling and offset-calibrated readout sense amplifiers in a fourth generation 10nm … DH Kim, B Song, H Ahn, W Ko, S Do, S Cho, K Kim, SH Oh, HY Joo, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 448-450, 2022 | 16 | 2022 |
| Duty cycle correction circuit and delay locked loop circuit including the same KH Kim, JB Koo US Patent 8,581,650, 2013 | 14 | 2013 |
| Variable unit delay circuit and clock generation circuit for semiconductor apparatus using the same KH Kim, DS Shin US Patent 8,330,512, 2012 | 11 | 2012 |
| Semiconductor integrated circuit WJ Yun, HW Lee, KH Kim US Patent 7,928,783, 2011 | 11 | 2011 |
| An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM with a hybrid-bank architecture, low power, and speed-boosting techniques CK Lee, HJ Chi, JS Heo, JH Park, JH Jang, D Lee, JH Jung, DH Lee, ... IEEE Journal of Solid-State Circuits 56 (1), 212-224, 2020 | 10 | 2020 |
| Duty correction circuit KH Kim, HW Lee US Patent 8,154,331, 2012 | 10 | 2012 |
| A 1.6 V 3.3 Gb/s GDDR3 DRAM with dual-mode phase-and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS HW Lee, WJ Yun, YK Choi, HH Choi, JJ Lee, KH Kim, SD Kang, JY Yang, ... 2009 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2009 | 8 | 2009 |
| An evaluation of the environmental effects of marine cage fish farms: I. Estimation of impact region and organic carbon cycling in sediment using sediment oxygen consumption … JS Lee, RH Jung, KH Kim, JN Kwon, WC Lee, PY Lee, JH Koo, WJ Choi J Korean Soc Oceanogr 9, 30-39, 2004 | 8 | 2004 |
| Semiconductor apparatus and DLL circuit using the same KH Kim, HW Lee US Patent 8,373,471, 2013 | 7 | 2013 |
| Data output control circuit KH Kim, HW Lee US Patent 8,487,679, 2013 | 6 | 2013 |
| A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration JS Heo, K Kim, DH Lee, CK Lee, DS Moon, K Kim, JH Baek, SW Yoon, ... 2019 Symposium on VLSI Circuits, C114-C115, 2019 | 4 | 2019 |
| Device characteristic compensation circuit and semiconductor apparatus using the same KH Kim, HW Lee US Patent 8,519,760, 2013 | 4 | 2013 |
| A low power and high performance robust digital delay locked loop against noisy environments HW Lee, WJ Yun, JJ Lee, KH Kim, NK Park, KW Kim, YJ Choi, JH Ahn, ... 2008 IEEE Asian Solid-State Circuits Conference, 241-244, 2008 | 4 | 2008 |
| Suppression of Digital Noise Coupling on LNA in 0.13-μm RFCMOS Technology by Global Guard Rings S Lee, K Kim, TH Oh, I Song, H Shin, M Kim, JS Rieh 2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF …, 2008 | 4 | 2008 |
| Semiconductor apparatus KH Kim, HW Lee, DH Kwon, CW Kim, SB Lim US Patent 8,836,370, 2014 | 2 | 2014 |
| Internal voltage generation circuit for semiconductor apparatus KH Kim, HW Lee, WJ Yun US Patent 8,390,364, 2013 | 2 | 2013 |
