| New generation of predictive technology model for sub-45 nm early design exploration W Zhao, Y Cao Electron Devices, IEEE Transactions on 53 (11), 2816-2823, 2006 | 1547 | 2006 |
| Predictive technology model for nano-CMOS design exploration W Zhao, Y Cao ACM Journal on Emerging Technologies in Computing Systems (JETC) 3 (1), 1-es, 2007 | 310 | 2007 |
| Rigorous extraction of process variations for 65-nm CMOS design W Zhao, F Liu, K Agarwal, D Acharyya, SR Nassif, KJ Nowka, Y Cao Semiconductor Manufacturing, IEEE Transactions on 22 (1), 196-203, 2009 | 146 | 2009 |
| Electrical characterization for intertier connections and timing analysis for 3-D ICs X Wu, W Zhao, M Nakamoto, C Nimmagadda, D Lisk, S Gu, R Radojcic, ... IEEE transactions on very large scale integration (VLSI) systems 20 (1), 186-191, 2010 | 89 | 2010 |
| Field-Based Capacitance Modeling for Sub-65-nm On-Chip Interconnect W Zhao, X Li, S Gu, SH Kang, MM Nowak, Y Cao Electron Devices, IEEE Transactions on 56 (9), 1862-1872, 2009 | 79 | 2009 |
| Optimizing FinFET technology for high-speed and low-power design T Sairam, W Zhao, Y Cao Proceedings of the 17th ACM Great Lakes symposium on VLSI, 73-77, 2007 | 56 | 2007 |
| Modeling of layout-dependent stress effect in CMOS design CC Wang, W Zhao, F Liu, M Chen, Y Cao Proceedings of the 2009 International Conference on Computer-Aided Design …, 2009 | 53* | 2009 |
| Simulation methodology and flow integration for 3D IC stress management M Nakamoto, R Radojcic, W Zhao, VK Dasarapu, AP Karmarkar, X Xu IEEE Custom Integrated Circuits Conference 2010, 1-4, 2010 | 45 | 2010 |
| Development of 3D through silicon stack (TSS) assembly for wide IO memory to logic devices integration DW Kim, R Vidhya, B Henderson, U Ray, S Gu, W Zhao, R Radojcic, ... 2013 IEEE 63rd Electronic Components and Technology Conference, 77-80, 2013 | 35 | 2013 |
| Finite-point-based transistor model: A new approach to fast circuit simulation M Chen, W Zhao, F Liu, Y Cao IEEE transactions on very large scale integration (VLSI) systems 17 (10 …, 2009 | 30* | 2009 |
| Via structure integrated in electronic substrate X Li, W Zhao, Y Cao, S Gu, SH Kang, MC King US Patent 8,227,708, 2012 | 19 | 2012 |
| The predictive technology model in the late silicon era and beyond Y Cao, A Balijepalli, S Sinha Now Publishers Inc 3 (4), 2010 | 16 | 2010 |
| Pathfinding for 22nm CMOS designs using predictive technology models X Li, W Zhao, Y Cao, Z Zhu, J Song, D Bang, CC Wang, SH Kang, J Wang, ... 2009 IEEE Custom Integrated Circuits Conference, 227-230, 2009 | 16 | 2009 |
| Predictive technology modeling for 32nm low power design W Zhao, X Li, M Nowak, Y Cao Semiconductor Device Research Symposium, 2007 International, 1-2, 2007 | 10 | 2007 |
| Carrier mobility shift in advanced silicon nodes due to chip-package interaction V Sukharev, JH Choy, A Kteyan, H Hovsepyan, M Nakamoto, W Zhao, ... Journal of Electronic Packaging 139 (2), 020906, 2017 | 9 | 2017 |
| PREDICTIVE MODELING OF CONTACT AND VIA MODULES FOR ADVANCED ON-CHIP INTERCONNECT TECHNOLOGY X Li, W Zhao, D Bang, Y Cao, SH Kang, M Nowak US Patent App. 12/493,110, 2009 | 9* | 2009 |
| Predictive modeling of interconnect modules for advanced on-chip interconnect technology X Li, W Zhao, Y Cao, S Gu, SH Kang, M Nowak US Patent 8,429,577, 2013 | 8 | 2013 |
| A field-based parasitic capacitance model with 3-D terminal and terminal fringe components A Zhang, W Zhao, Y Hu, J He, Q He, L Song, H Zhou, Y Wu 2015 6th Asia Symposium on Quality Electronic Design (ASQED), 166-170, 2015 | 7 | 2015 |
| Mechanical stress management for electrical chip-package interaction (e-CPI) W Zhao, M Nakamoto, V Ramachandran, R Radojcic 2014 IEEE 64th Electronic Components and Technology Conference (ECTC), 1226-1230, 2014 | 5 | 2014 |
| Efficient variation-aware delay fault simulation methodology for resistive open and bridge defects S Zhong, S Khursheed, BM Al-Hashimi, W Zhao IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014 | 5 | 2014 |