| Newton: A DRAM-maker’s accelerator-in-memory (AiM) architecture for machine learning M He, C Song, I Kim, C Jeong, S Kim, I Park, M Thottethodi, ... 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture …, 2020 | 155 | 2020 |
| A 1ynm 1.25 V 8Gb, 16Gb/s/pin GDDR6-based accelerator-in-memory supporting 1TFLOPS MAC operation and various activation functions for deep-learning applications S Lee, K Kim, S Oh, J Park, G Hong, D Ka, K Hwang, J Park, K Kang, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 91 | 2022 |
| High bandwidth memory (HBM) with TSV technique JC Lee, J Kim, KW Kim, YJ Ku, DS Kim, C Jeong, TS Yun, H Kim, HS Cho, ... 2016 International SoC Design Conference (ISOCC), 181-182, 2016 | 57 | 2016 |
| A 1.2 V 64Gb 341GB/S HBM2 stacked DRAM with spiral point-to-point TSV structure and improved bank group data control JH Cho, J Kim, WY Lee, DU Lee, TK Kim, HB Park, C Jeong, MJ Park, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 208-210, 2018 | 49 | 2018 |
| Clock data recovery apparatus CS Jeong, JJ Lee, C Yoo, JJ Park, YS Seo US Patent 7,826,583, 2010 | 44 | 2010 |
| Band-gap reference voltage generator SJ Kim, CS Jeong US Patent 7,570,107, 2009 | 39 | 2009 |
| Open-loop full-digital duty cycle correction circuit C Yoo, C Jeong, J Kih Electronics letters 41 (11), 635-636, 2005 | 37 | 2005 |
| Circuit and method of outputting temperature data of semiconductor memory apparatus CS Jeong, KS Lee US Patent 7,643,889, 2010 | 36 | 2010 |
| 18.3 A 1.2 V 64Gb 8-channel 256GB/s HBM DRAM with peripheral-base-die architecture and small-swing technique on heavy load interface JC Lee, J Kim, KW Kim, YJ Ku, DS Kim, C Jeong, TS Yun, H Kim, HS Cho, ... 2016 IEEE International Solid-State Circuits Conference (ISSCC), 318-319, 2016 | 33 | 2016 |
| A 5-Gbit/s Clock- and Data-Recovery Circuit With 1/8-Rate Linear Phase Detector in 0.18- CMOS Technology YS Seo, JW Lee, HJ Kim, C Yoo, JJ Lee, CS Jeong IEEE Transactions on Circuits and Systems II: Express Briefs 56 (1), 6-10, 2009 | 32 | 2009 |
| 22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a pseudo quarter bank structure, power dispersion and an instruction-based at-speed PMBIST DU Lee, HS Cho, J Kim, YJ Ku, S Oh, CD Kim, HW Kim, WY Lee, TK Kim, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 334-336, 2020 | 31 | 2020 |
| On die thermal sensor of semiconductor memory device and method thereof CS Jeong US Patent 7,451,053, 2008 | 31 | 2008 |
| System architecture and software stack for GDDR6-AiM Y Kwon, K Vladimir, N Kim, W Shin, J Won, M Lee, H Joo, H Choi, G Kim, ... 2022 IEEE Hot Chips 34 Symposium (HCS), 1-25, 2022 | 29 | 2022 |
| On die thermal sensor CS Jeong, KT Park US Patent 8,140,293, 2012 | 27 | 2012 |
| Phase detector, phase-frequency detector, and digital phase locked loop YH Kim, J Soo-Young, C Yoo, CS Jeong, KS Lee US Patent 9,337,849, 2016 | 22 | 2016 |
| Digital delay locked loop with open-loop digital duty cycle corrector for 1.2 Gb/s/pin double data rate SDRAM C Jeong, C Yoo, JJ Lee, J Kih Proceedings of the 30th European Solid-State Circuits Conference, 379-382, 2004 | 22 | 2004 |
| Impedance matching circuit and semiconductor memory device with the same CS Jeong, JJ Lee US Patent 7,710,143, 2010 | 21 | 2010 |
| Semiconductor memory apparatus and method for correcting duty thereof YH Kim, CS Jeong US Patent 8,513,996, 2013 | 19 | 2013 |
| On die thermal sensor CS Jeong, KT Park US Patent 7,965,571, 2011 | 19 | 2011 |
| Impedance adjusting circuit and semiconductor memory device having the same CS Jeong, KS Lee US Patent 7,642,808, 2010 | 18 | 2010 |