| RevLib: An online resource for reversible functions and reversible circuits R Wille, D Große, L Teuber, GW Dueck, R Drechsler 38th International Symposium on Multiple Valued Logic (ismvl 2008), 220-225, 2008 | 588 | 2008 |
| Exact multiple-control Toffoli network synthesis with SAT techniques D Große, R Wille, GW Dueck, R Drechsler IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009 | 224 | 2009 |
| Proving transaction and system-level properties of untimed SystemC TLM designs D Große, HM Le, R Drechsler Eighth ACM/IEEE International Conference on Formal Methods and Models for …, 2010 | 111 | 2010 |
| Formal verification of integer multipliers by combining Gröbner basis with logic reduction A Sayed-Ahmed, D Große, U Kühne, M Soeken, R Drechsler 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2016 | 106 | 2016 |
| Equivalence checking of reversible circuits R Wille, D Große, DM Miller, R Drechsler 2009 39th International Symposium on Multiple-Valued Logic, 324-330, 2009 | 97 | 2009 |
| HW/SW co-verification of embedded systems using bounded model checking D Große, U Kühne, R Drechsler Proceedings of the 16th ACM Great Lakes symposium on VLSI, 43-48, 2006 | 87 | 2006 |
| Extensible and configurable RISC-V based virtual prototype V Herdt, D Große, HM Le, R Drechsler 2018 Forum on Specification & Design Languages (FDL), 5-16, 2018 | 82 | 2018 |
| Approximation-aware rewriting of AIGs for error tolerant applications A Chandrasekharan, M Soeken, D Große, R Drechsler 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2016 | 78 | 2016 |
| BDD minimization for approximate computing M Soeken, D Große, A Chandrasekharan, R Drechsler 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 474-479, 2016 | 74 | 2016 |
| RISC-V based virtual prototype: An extensible and configurable platform for the system-level V Herdt, D Große, P Pieper, R Drechsler Journal of Systems Architecture 109, 101756, 2020 | 73 | 2020 |
| Verifying SystemC using an intermediate verification language and symbolic simulation HM Le, D Große, V Herdt, R Drechsler Proceedings of the 50th Annual Design Automation Conference, 1-6, 2013 | 72 | 2013 |
| RevSCA: Using reverse engineering to bring light into backward rewriting for big and dirty multipliers A Mahzoon, D Große, R Drechsler Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 71 | 2019 |
| Quantified synthesis of reversible logic R Wille, HM Le, GW Dueck, D Große 2008 Design, Automation and Test in Europe, 1015-1020, 2008 | 71 | 2008 |
| Quality-driven SystemC design D Große, R Drechsler Springer, 2010 | 70 | 2010 |
| SWORD: A SAT like prover using word level information R Wille, G Fey, D Große, D Große, S Eggersglüß, R Drechsler VLSI-SoC: Advanced Topics on Systems on a Chip: A Selection of Extended …, 2009 | 70 | 2009 |
| Formal verification of LTL formulas for SystemC designs D Große, R Drechsler Proceedings of the 2003 International Symposium on Circuits and Systems …, 2003 | 63 | 2003 |
| PolyCleaner: clean your polynomials before backward rewriting to verify million-gate multipliers A Mahzoon, D Große, R Drechsler 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2018 | 62 | 2018 |
| Exact SAT-based Toffoli network synthesis D Große, X Chen, GW Dueck, R Drechsler Proceedings of the 17th ACM Great Lakes symposium on VLSI, 96-101, 2007 | 62 | 2007 |
| An exact method for design exploration of quantum-dot cellular automata M Walter, R Wille, D Große, FS Torres, R Drechsler 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 503-508, 2018 | 61 | 2018 |
| Reachability analysis for formal verification of SystemC R Drechsler, D Große Proceedings Euromicro Symposium on Digital System Design. Architectures …, 2002 | 60 | 2002 |
Rolf DrechslerProfessor at University of Bremen, Director DFKI Bremen, GermanyVerified email at uni-bremen.de
