| First-order temporal logic monitoring with BDDs K Havelund, D Peled, D Ulus Formal Methods in System Design 56 (1), 1-21, 2020 | 87 | 2020 |
| Timed pattern matching D Ulus, T Ferrère, E Asarin, O Maler International Conference on Formal Modeling and Analysis of Timed Systems …, 2014 | 79 | 2014 |
| AMT 2.0: qualitative and quantitative trace analysis with extended signal temporal logic D Ničković, O Lebeltel, O Maler, T Ferrère, D Ulus International Journal on Software Tools for Technology Transfer 22, 741-758, 2020 | 61 | 2020 |
| Online timed pattern matching using derivatives D Ulus, T Ferrère, E Asarin, O Maler Tools and Algorithms for the Construction and Analysis of Systems: 22nd …, 2016 | 60 | 2016 |
| Montre: A Tool for Monitoring Timed Regular Expressions D Ulus Computer Aided Verification: 29th International Conference, CAV 2017 …, 2017 | 49 | 2017 |
| On the quantitative semantics of regular expressions over real-valued signals A Bakhirkin, T Ferrère, O Maler, D Ulus International Conference on Formal Modeling and Analysis of Timed Systems …, 2017 | 29 | 2017 |
| Measuring with timed patterns T Ferrère, O Maler, D Ničković, D Ulus Computer Aided Verification: 27th International Conference, CAV 2015, San …, 2015 | 28 | 2015 |
| Special session: Embedded software for robotics: Challenges and future directions H Abbas, I Saha, Y Shoukry, R Ehlers, G Fainekos, R Gupta, R Majumdar, ... 2018 International Conference on Embedded Software (EMSOFT), 1-10, 2018 | 22* | 2018 |
| DejaVu: a monitoring tool for first-order temporal logic K Havelund, D Peled, D Ulus 2018 IEEE Workshop on Monitoring and Testing of Cyber-Physical Systems (MT …, 2018 | 19 | 2018 |
| Online monitoring of metric temporal logic using sequential networks D Ulus arXiv preprint arXiv:1901.00175, 2019 | 18 | 2019 |
| Timescales: A benchmark generator for MTL monitoring tools D Ulus Runtime Verification: 19th International Conference, RV 2019, Porto …, 2019 | 17 | 2019 |
| Derivatives of quantitative regular expressions R Alur, K Mamouras, D Ulus Models, Algorithms, Logics and Tools: Essays Dedicated to Kim Guldstrand …, 2017 | 17 | 2017 |
| Specifying timed patterns using temporal logic D Ulus, O Maler Proceedings of the 21st International Conference on Hybrid Systems …, 2018 | 14 | 2018 |
| First-order Temporal Logic Monitoring with BDDs, FMCAD’17 K Havelund, D Peled, D Ulus IEEE, 2017 | 10 | 2017 |
| Reactive control meets runtime verification: A case study of navigation D Ulus, C Belta Runtime Verification: 19th International Conference, RV 2019, Porto …, 2019 | 9 | 2019 |
| Combining the temporal and epistemic dimensions for MTL monitoring E Asarin, O Maler, D Nickovic, D Ulus International Conference on Formal Modeling and Analysis of Timed Systems …, 2017 | 7 | 2017 |
| Using haloes in mixed-signal assertion based verification D Ulus, A Sen 2012 IEEE International High Level Design Validation and Test Workshop …, 2012 | 6 | 2012 |
| Sequential circuits from regular expressions revisited D Ulus arXiv preprint arXiv:1801.08979, 2018 | 5 | 2018 |
| Pattern Matching with Time: Theory and Applications D Ulus Universite Grenoble-Alpes (UGA), 2018 | 4 | 2018 |
| On the complexity of timed pattern matching E Asarin, T Ferrère, D Ničković, D Ulus International Conference on Formal Modeling and Analysis of Timed Systems, 15-31, 2021 | 2 | 2021 |
Oded MalerCNRS-VERIMAG, University of GrenobleVerified email at imag.fr