| Design methodologies based on hardware description languages T Riesgo, Y Torroja, E De la Torre IEEE Transactions on Industrial electronics 46 (1), 3-12, 1999 | 133 | 1999 |
| A modular architecture for nodes in wireless sensor networks. J Portilla, A De Castro, E De La Torre, T Riesgo J. Univers. Comput. Sci. 12 (3), 328-339, 2006 | 114 | 2006 |
| FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo3 Framework A Rodríguez, J Valverde, J Portilla, A , Otero, T Riesgo, E de la Torre Sensors 18 (6), 1-30, 2018 | 100 | 2018 |
| Embedded runtime reconfigurable nodes for wireless sensor networks applications YE Krasteva, J Portilla, E de la Torre, T Riesgo IEEE Sensors Journal 11 (9), 1800-1810, 2011 | 92 | 2011 |
| Using SRAM based FPGAs for power-aware high performance wireless sensor networks J Valverde, A Otero, M Lopez, J Portilla, E De la Torre, T Riesgo Sensors 12 (3), 2667-2692, 2012 | 75 | 2012 |
| Self-reconfigurable Evolvable Hardware System for Adaptive Image Processing R Salvador, A Otero, J Mora, E de la Torre, T Riesgo, L Sekanina Transactions on Computers, 1-1, 2013 | 72 | 2013 |
| Adaptable security in wireless sensor networks by using reconfigurable ECC hardware coprocessors J Portilla, A Otero, E de la Torre, T Riesgo, O Stecklina, S Peter, ... International Journal of Distributed Sensor Networks 6 (1), 740823, 2010 | 68 | 2010 |
| FPGAs: fundamentals, advanced features, and applications in industrial electronics JJR Andina, E De la Torre Arnanz, MDV Peña CRC Press, 2017 | 67 | 2017 |
| Virtex II FPGA bitstream manipulation: Application to reconfiguration control systems YE Krasteva, E De La Torre, T Riesgo, D Joly 2006 International Conference on Field Programmable Logic and Applications, 1-4, 2006 | 62 | 2006 |
| Fault tolerance analysis and self-healing strategy of autonomous, evolvable hardware systems R Salvador, A Otero, J Mora, E de la Torre, L Sekanina, T Riesgo 2011 International Conference on Reconfigurable Computing and FPGAs, 164-169, 2011 | 61 | 2011 |
| A fast emulation-based NoC prototyping framework YE Krasteva, F Criado, E de la Torre, T Riesgo 2008 International Conference on Reconfigurable Computing and FPGAs, 211-216, 2008 | 53 | 2008 |
| Straight method for reallocation of complex cores by dynamic reconfiguration in Virtex II FPGAs YE Krasteva, AB Jimeno, E de la Torre, T Riesgo 16th IEEE International Workshop on Rapid System Prototyping (RSP'05), 77-83, 2005 | 53 | 2005 |
| Remote HW-SW reconfigurable wireless sensor nodes YE Krasteva, J Portilla, JM Carnicer, E de la Torre, T Riesgo Industrial Electronics, 2008. IECON 2008. 34th Annual Conference of IEEE …, 2008 | 51 | 2008 |
| A machine-learning-based distributed system for fault diagnosis with scalable detection quality in industrial IoT R Marino, C Wisultschew, A Otero, JM Lanza-Gutierrez, J Portilla, ... IEEE Internet of Things Journal 8 (6), 4339-4352, 2020 | 46 | 2020 |
| Dreams: A tool for the design of dynamically reconfigurable embedded and modular systems A Otero, E de la Torre, T Riesgo 2012 International Conference on Reconfigurable Computing and FPGAs, 1-8, 2012 | 46 | 2012 |
| Run-time reconfigurable MPSoC-based on-board processor for vision-based space navigation A Pérez, A Rodríguez, A Otero, DG Arjona, A Jiménez-Peralo, ... IEEE Access 8, 59891-59905, 2020 | 41 | 2020 |
| Cross-layer design of reconfigurable cyber-physical systems M Masin, F Palumbo, H Myrhaug, JA de Oliveira Filho, M Pastena, ... Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017 | 38 | 2017 |
| Scalable hardware-based on-board processing for run-time adaptive lossless hyperspectral compression A Rodriguez, L Santos, R Sarmiento, E De La Torre IEEE Access 7, 10644-10652, 2019 | 36 | 2019 |
| A precharge-absorbed DPL logic for reducing early propagation effects on FPGA implementations W He, E de la Torre, T Riesgo 2011 International Conference on Reconfigurable Computing and FPGAs, 217-222, 2011 | 34 | 2011 |
| Automatic generation of identical routing pairs for FPGA implemented DPL logic W He, A Otero, E de la Torre, T Riesgo 2012 International Conference on Reconfigurable Computing and FPGAs, 1-6, 2012 | 33 | 2012 |
Teresa RiesgoUniversidad Politecnica de Madrid / Ministerio de Ciencia, Innovación y UniversidadesVerified email at upm.es