| Acceleration of the Secure Hash Algorithm-256 (SHA-256) on an FPGA-CPU Cluster Using OpenCL H Bensalem, Y Blaquière, Y Savaria 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2021 | 18 | 2021 |
| An Efficient OpenCL-Based Implementation of a SHA-3 Co-Processor on an FPGA-Centric Platform H Bensalem, Y Blaquière, Y Savaria IEEE Transactions on Circuits and Systems II: Express Briefs, 2022 | 8 | 2022 |
| In-FPGA Instrumentation Framework for OpenCL-Based Designs H Bensalem, Y Blaquière, Y Savaria IEEE Access 8, 212979-212994, 2020 | 6 | 2020 |
| Toward in-system monitoring of OpenCL-based designs on FPGA H Bensalem, Y Blaquière, Y Savaria 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019 | 5 | 2019 |
| A BinDCT hardware accelerator design and integration on a SOPC AB Abdelali, R Hmida, HB Salem, S Manaaï, A Mtibaa International Conference on Embedded Systems and Applications, 2014 | | 2014 |
Yves BlaquièreEcole de technologie superieureVerified email at etsmtl.ca