| Corner block list: An effective and efficient topological representation of non-slicing floorplan X Hong, G Huang, Y Cai, J Gu, S Dong, CK Cheng, J Gu IEEE/ACM International Conference on Computer Aided Design. ICCAD-2000. IEEE …, 2000 | 481 | 2000 |
| UNISM: Unified scheduling and mapping for general networks on chip O He, S Dong, W Jang, J Bian, DZ Pan IEEE transactions on very large scale integration (VLSI) systems 20 (8 …, 2011 | 89 | 2011 |
| Optimal two-dimension common centroid layout generation for MOS transistors unit-circuit D Long, X Hong, S Dong 2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2999-3002, 2005 | 59 | 2005 |
| Corner block list representation and its application to floorplan optimization X Hong, S Dong, G Huang, Y Cai, CK Cheng, J Gu IEEE Transactions on Circuits and Systems II: Express Briefs 51 (5), 228-233, 2004 | 59 | 2004 |
| VLSI floorplanning with boundary constraints based on corner block list Y Ma, S Dong, X Hong, Y Cai, CK Cheng, J Gu Proceedings of the 2001 Asia and South Pacific Design Automation Conference …, 2001 | 58 | 2001 |
| ECBL: An extended corner block list with solution space including optimum placement S Zhou, S Dong, CK Cheng, J Gu Proceedings of the 2001 international symposium on Physical design, 150-155, 2001 | 54 | 2001 |
| Floorplanning and topology generation for application-specific network-on-chip B Yu, S Dong, S Chen, S Goto 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 535-540, 2010 | 52 | 2010 |
| 3D CBL: An efficient algorithm for general 3D packing problems Y Ma, X Hong, S Dong, CK Cheng 48th Midwest Symposium on Circuits and Systems, 2005., 1079-1082, 2005 | 47 | 2005 |
| Floorplanning with abutment constraints and L-shpaed/T-shaped blocks baed on corner block list Y Ma, X Hong, S Dong, Y Cai, CK Cheng, J Gu Proceedings of the 38th annual Design Automation Conference, 770-775, 2001 | 45 | 2001 |
| LP based white space redistribution for thermal via planning and performance optimization in 3D ICs X Li, Y Ma, X Hong, S Dong, J Cong 2008 Asia and South Pacific Design Automation Conference, 209-212, 2008 | 37 | 2008 |
| Simultaneous buffer and interlayer via planning for 3D floorplanning X He, S Dong, Y Ma, X Hong 2009 10th International Symposium on Quality Electronic Design, 740-745, 2009 | 35 | 2009 |
| A novel fixed-outline floorplanner with zero deadspace for hierarchical design O He, S Dong, J Bian, S Goto, CK Cheng 2008 IEEE/ACM International Conference on Computer-Aided Design, 16-23, 2008 | 31 | 2008 |
| Signal-path driven partition and placement for analog circuit D Long, X Hong, S Dong Proceedings of the 2006 Asia and South Pacific Design Automation Conference …, 2006 | 29 | 2006 |
| Thermal-driven symmetry constraint for analog layout with CBL representation J Liu, S Dong, Y Ma, D Long, X Hong 2007 Asia and South Pacific Design Automation Conference, 191-196, 2007 | 28 | 2007 |
| VLSI block placement using less flexibility first principles S Dong, X Hong, Y Wu, Y Lin, J Gu Proceedings of the 2001 Asia and South Pacific design automation conference …, 2001 | 27 | 2001 |
| Delay-driven layer assignment in global routing under multi-tier interconnect structure J Ao, S Dong, S Chen, S Goto Proceedings of the 2013 ACM International symposium on Physical Design, 101-107, 2013 | 26 | 2013 |
| Buffer planning as an integral part of floorplanning with consideration of routing congestion Y Ma, X Hong, S Dong, S Chen, CK Cheng, J Gu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2005 | 26 | 2005 |
| Dynamic global buffer planning optimization based on detail block locating and congestion analysis Y Ma, X Hong, S Dong, S Chen, Y Cai, CK Cheng, J Gu Proceedings of the 40th annual Design Automation Conference, 806-811, 2003 | 25 | 2003 |
| Application-specific network-on-chip synthesis: Cluster generation and network component insertion W Zhong, B Yu, S Chen, T Yoshimura, S Dong, S Goto 2011 12th International Symposium on Quality Electronic Design, 1-6, 2011 | 22 | 2011 |
| Symmetry constraint based on mismatch analysis for analog layout in SOI technology J Liu, S Dong, X Hong, Y Wang, O He, S Goto 2008 Asia and South Pacific Design Automation Conference, 772-775, 2008 | 22 | 2008 |
