| A 10-Gb/s 5-tap DFE/4-tap FFE transceiver in 90-nm CMOS technology JF Bulzacchelli, M Meghelli, SV Rylov, W Rhee, AV Rylyakov, HA Ainspan, ... IEEE Journal of Solid-State Circuits 41 (12), 2885-2900, 2006 | 319 | 2006 |
| Silicon Heterostructure Handbook: Materials, Fabrication, Devices, Circuits and Applications of SiGe and Si Strained-Layer Epitaxy JD Cressler, S Monfray, G Freeman, D Friedman, DJ Paul, S Tsujino, ... CRC press, 2018 | 302 | 2018 |
| A 0.18/spl mu/m BiCMOS technology featuring 120/100 GHz (f/sub T//f/sub max/) HBT and ASIC-compatible CMOS using copper interconnect A Joseph, D Coolbaugh, M Zierak, R Wuthrich, P Geiss, Z He, X Liu, ... Proceedings of the 2001 BIPOLAR/BiCMOS Circuits and Technology Meeting (Cat …, 2001 | 175 | 2001 |
| SiGe heterojunction bipolar transistors and circuits toward terahertz communication applications JS Rieh, B Jagannathan, DR Greenberg, M Meghelli, A Rylyakov, ... IEEE transactions on Microwave Theory and Techniques 52 (10), 2390-2408, 2004 | 122 | 2004 |
| SiGe HBT technology with f/sub max//f/sub T/= 350/300 GHz and gate delay below 3.3 ps M Khater, JS Rieh, T Adam, A Chinthakindi, J Johnson, R Krishnasamy, ... IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004 | 120 | 2004 |
| A 10-Gb/s two-dimensional eye-opening monitor in 0.13-/spl mu/m standard CMOS B Analui, A Rylyakov, S Rylov, M Meghelli, A Hajimiri IEEE Journal of Solid-State Circuits 40 (12), 2689-2699, 2005 | 94 | 2005 |
| Packaging optoelectronic components and CMOS circuitry using silicon-on-insulator substrates for photonics applications RA Budd, M Meghelli, JS Orcutt, JO Plouchart US Patent 9,786,641, 2017 | 93 | 2017 |
| 40-Gb/s circuits built from a 120-GHz f/sub T/SiGe technology G Freeman, M Meghelli, Y Kwark, S Zier, A Rylyakov, MA Sorna, T Tanji, ... IEEE Journal of Solid-State Circuits 37 (9), 1106-1114, 2002 | 86 | 2002 |
| A 128-Gb/s 1.3-pJ/b PAM-4 transmitter with reconfigurable 3-tap FFE in 14-nm CMOS Z Toprak-Deniz, JE Proesel, JF Bulzacchelli, HA Ainspan, TO Dickson, ... IEEE Journal of Solid-State Circuits 55 (1), 19-26, 2019 | 79 | 2019 |
| SiGe BiCMOS 3.3-V clock and data recovery circuits for 10-Gb/s serial transmission systems M Meghelli, B Parker, H Ainspan, M Soyuer IEEE Journal of Solid-State Circuits 35 (12), 1992-1995, 2000 | 79 | 2000 |
| A 25 Gb/s burst-mode receiver for low latency photonic switch networks A Rylyakov, JE Proesel, S Rylov, BG Lee, JF Bulzacchelli, A Ardey, ... IEEE Journal of Solid-State Circuits 50 (12), 3120-3132, 2015 | 77 | 2015 |
| A 10Gb/s 5-tap-DFE/4-tap-FFE transceiver in 90nm CMOS M Meghelli, S Rylov, J Bulzacchelli, W Rhee, A Rylyakov, H Ainspan, ... 2006 IEEE International Solid State Circuits Conference-Digest of Technical …, 2006 | 75 | 2006 |
| A 64-Gb/s 1.4-pJ/b NRZ optical receiver data-path in 14-nm CMOS FinFET I Ozkaya, A Cevrero, PA Francese, C Menolfi, T Morf, M Brändli, ... IEEE Journal of Solid-State Circuits 52 (12), 3458-3473, 2017 | 73 | 2017 |
| 50-Gb/s SiGe BiCMOS 4: 1 multiplexer and 1: 4 demultiplexer for serial communication systems M Meghelli, AV Rylyakov, L Shan IEEE Journal of Solid-State Circuits 37 (12), 1790-1794, 2002 | 73 | 2002 |
| A 0.18-μm SiGe BiCMOS receiver and transmitter chipset for SONET OC-768 transmission systems M Meghelli, AV Rylyakov, SJ Zier, M Sorna, D Friedman IEEE Journal of Solid-State Circuits 38 (12), 2147-2154, 2003 | 72 | 2003 |
| 132-Gb/s 4: 1 multiplexer in 0.13-/spl mu/m SiGe-bipolar technology M Meghelli IEEE Journal of Solid-State Circuits 39 (12), 2403-2407, 2004 | 71 | 2004 |
| A 32 Gb/s, 4.7 pJ/bit optical link with− 11.7 dBm sensitivity in 14-nm FinFET CMOS JE Proesel, Z Toprak-Deniz, A Cevrero, I Ozkaya, S Kim, DM Kuchta, ... IEEE Journal of Solid-State Circuits 53 (4), 1214-1226, 2017 | 70 | 2017 |
| Phase and amplitude pre-emphasis techniques for low-power serial links JF Buckwalter, M Meghelli, DJ Friedman, A Hajimiri IEEE Journal of solid-state circuits 41 (6), 1391-1399, 2006 | 65 | 2006 |
| A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology GR Gangasani, CM Hsu, JF Bulzacchelli, S Rylov, T Beukema, D Freitas, ... IEEE journal of solid-state circuits 47 (8), 1828-1841, 2012 | 64 | 2012 |
| An integrated silicon photonics technology for O-band datacom NB Feilchenfeld, FG Anderson, T Barwicz, S Chilstedt, Y Ding, ... 2015 IEEE International Electron Devices Meeting (IEDM), 25.7. 1-25.7. 4, 2015 | 61 | 2015 |
