| Implementation of BIST structure using VHDL for VLSI circuits S Jamuna, VK Agrawal International Journal of Engineering Science and Technology 3 (6), 2011 | 14 | 2011 |
| Design and Implementation of BIST logic for ALU on FPGA S Jamuna, P Dinesha, K Shashikala 2018 International Conference on Networking, Embedded and Wireless Systems …, 2018 | 8 | 2018 |
| Implementation of bistcontroller for fault detection in clb of fpga S Jamuna, VK Agrawal 2012 International Conference on Devices, Circuits and Systems (ICDCS), 99-104, 2012 | 8 | 2012 |
| Design of fault injection technique for VLSI digital circuits BJ Lavanyashree, S Jamuna 2017 2nd IEEE International Conference on Recent Trends in Electronics …, 2017 | 7 | 2017 |
| Area optimized run-time reconfigurable ALU for digital systems S Jamuna, P Dinesha, K Shashikala, KK Kumar 2019 Second International Conference on Advanced Computational and …, 2019 | 5 | 2019 |
| Hardware Resource Optimization for Embedded System Design: A Brief Review YJ Pavitra, S Jamuna, J Manikandan 2018 3rd International Conference for Convergence in Technology (I2CT), 1-6, 2018 | 5 | 2018 |
| VHDL implementation of BIST controller S Jamuna, VK Agrawal 3rd International Conference on Advances in Recent Technologies in …, 2011 | 5 | 2011 |
| Design of combinational logic circuits using simulated annealing YJ Pavitra, S Jamuna, J Manikandan, E Arun 2022 International Conference for Advancement in Technology (ICONAT), 1-6, 2022 | 4 | 2022 |
| A Brief Review on Multiple-Valued Logic-based Digital Circuits Nagarathna, S Jamuna ICT with Intelligent Applications: Proceedings of ICTIS 2021, Volume 1, 329-337, 2022 | 4 | 2022 |
| Design and implementation of reliable encryption algorithms through soft error mitigation S Jamuna, P Dinesha, K Shashikala, KK Kishore International Journal of Computer Network and Information Security 12 (4), 41-50, 2020 | 4 | 2020 |
| Detection and Diagnosis of Faults in the Routing Resources of a SRAM based FPGAs S Jamuna, VK Agrawal International Journal of Computer Applications 53 (13), 2012 | 3 | 2012 |
| Design and Comparative Analysis of Various Sram Cells Using 16 Nm Technology Node S Sampath, DC Chinvar, S Chandrashekhar, S Jamuna 2022 3rd International Conference for Emerging Technology (INCET), 1-5, 2022 | 2 | 2022 |
| A brief review on types and design methods of ADC S Jamuna, P Dinesha, KP Shashikala J. Eng. Res. Appl. 8 (6), 85-91, 2018 | 2 | 2018 |
| Dynamic reconfigurable modulator for communication systems S Jamuna, P Dinesha, K Shashikala 2018 International Conference on Networking, Embedded and Wireless Systems …, 2018 | 1 | 2018 |
| Study and Evaluation of Digital Circuit Design Using Evolutionary Algorithm YJ Pavitra, E Arun, S Jamuna, J Manikandan 2018 15th IEEE India Council International Conference (INDICON), 1-5, 2018 | 1 | 2018 |
| Implementation of Advanced Encryption standard in Vivado Design suite DP Divya, S Jamuna JEITR, 2018 | 1 | 2018 |
| Design and Simulation of Data Acquisition system using Ethernet for Zynq 7000 SoC FPGA P Angadi, S Satwika, E Shreya, S Jamuna 2024 16th International Conference on Electronics, Computers and Artificial …, 2024 | | 2024 |
| Realization and Optimization of Combinational Circuits Using Simulated Annealing and Partitioning Approach YJ Pavitra, S Jamuna, J Manikandan IETE Journal of Research 70 (4), 4137-4148, 2024 | | 2024 |
| Design and Evaluation of Arithmetic and Logic Unit Using Simulated Annealing YJ Pavitra, S Jamuna, J Manikandan 2023 10th International Conference on Soft Computing & Machine Intelligence …, 2023 | | 2023 |
| Design and Comparative Analysis of Novel 8T and 6T SRAM Cell Using 16 nm Technology S Jamuna, S Sampath, C Srinivas, DC Chinvar, GS Bhargav, ... International Conference on VLSI, Signal Processing, Power Electronics, IoT …, 2023 | | 2023 |