| The gem5 simulator N Binkert, B Beckmann, G Black, SK Reinhardt, A Saidi, A Basu, ... ACM SIGARCH computer architecture news 39 (2), 1-7, 2011 | 6186 | 2011 |
| Rerun: Exploiting episodes for lightweight memory race recording DR Hower, MD Hill ACM SIGARCH computer architecture news 36 (3), 265-276, 2008 | 221 | 2008 |
| Heterogeneous-race-free memory models DR Hower, BA Hechtman, BM Beckmann, BR Gaster, MD Hill, ... Proceedings of the 19th international conference on Architectural support …, 2014 | 131 | 2014 |
| Calvin: Deterministic or not? free will to choose DR Hower, P Dudnik, MD Hill, DA Wood 2011 IEEE 17th International Symposium on High Performance Computer …, 2011 | 101 | 2011 |
| QuickRelease: A throughput-oriented approach to release consistency on GPUs BA Hechtman, S Che, DR Hower, Y Tian, BM Beckmann, MD Hill, ... 2014 IEEE 20th International Symposium on High Performance Computer …, 2014 | 88 | 2014 |
| The Gem5 Simulator. SIGARCH Comput. Archit. News 39, 2 (Aug. 2011), 1–7 N Binkert, B Beckmann, G Black, SK Reinhardt, A Saidi, A Basu, ... | 81 | 2011 |
| HRF-Relaxed: Adapting HRF to the complexities of industrial heterogeneous memory models BR Gaster, D Hower, L Howes ACM Transactions on Architecture and Code Optimization (TACO) 12 (1), 1-26, 2015 | 46 | 2015 |
| Two hardware-based approaches for deterministic multiprocessor replay DR Hower, P Montesinos, L Ceze, MD Hill, J Torrellas Communications of the ACM 52 (6), 93-100, 2009 | 40 | 2009 |
| A Case for Deconstructing Hardware Transactional Memory Systems MD Hill, D Hower, KE Moore, MM Swift, H Volos, DA Wood Dagstuhl Seminar Proceedings, 2007 | 26 | 2007 |
| Self-checking and self-diagnosing 32-bit microprocessor multiplier M Yilmaz, DR Hower, S Ozev, DJ Sorin 2006 IEEE International Test Conference, 1-10, 2006 | 23 | 2006 |
| System and method for repurposing dead cache blocks GH Loh, DR Hower, S Che US Patent 9,990,289, 2018 | 20 | 2018 |
| TLB shootdown mitigation for low-power many-core servers with L1 virtual caches B Pham, D Hower, A Bhattacharjee, T Cain IEEE Computer Architecture Letters 17 (1), 17-20, 2017 | 18 | 2017 |
| Pabst: Proportionally allocated bandwidth at the source and target DR Hower, HW Cain, CA Waldspurger 2017 IEEE International Symposium on High Performance Computer Architecture …, 2017 | 17 | 2017 |
| FreshCache: Statically and dynamically exploiting dataless ways A Basu, DR Hower, MD Hill, MM Swift 2013 IEEE 31st International Conference on Computer Design (ICCD), 286-293, 2013 | 16 | 2013 |
| Efficient load value prediction using multiple predictors and filters R Sheikh, D Hower 2019 IEEE International Symposium on High Performance Computer Architecture …, 2019 | 15 | 2019 |
| Method and apparatus for cache line deduplication via data matching HW Cain III, DR Hower, R Damodaran, TA Sartorius US Patent App. 14/865,049, 2017 | 15 | 2017 |
| Applying architectural vulnerability analysis to hard faults in the microprocessor FA Bower, D Hower, M Yilmaz, DJ Sorin, S Ozev Proceedings of the joint international conference on Measurement and …, 2006 | 15 | 2006 |
| Jenga: Efficient fault tolerance for stacked dram G Mappouras, A Vahid, R Calderbank, DR Hower, DJ Sorin 2017 IEEE International Conference on Computer Design (ICCD), 361-368, 2017 | 12 | 2017 |
| Method for memory consistency among heterogeneous computer components DR Hower, MD Hill, D Wood, SK Reinhardt, BR Gaster, BA Hechtman, ... US Patent 9,361,118, 2016 | 9 | 2016 |
| Allocating power between multiple central processing units (CPUs) in a multi-CPU processor based on total current availability and individual CPU quality-of-service (QoS … S Priyadarshi, SM Zahedi, DR Hower, CA Waldspurger, JT Bridges, ... US Patent 10,831,254, 2020 | 8 | 2020 |
Mark D. HillUniversity of Wisconsin-Madison Professor EmeritusVerified email at cs.wisc.edu
