| 16.4 An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications YD Chih, PH Lee, H Fujiwara, YC Shih, CF Lee, R Naous, YL Chen, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 252-254, 2021 | 251 | 2021 |
| 16.1 A 22nm 4Mb 8b-precision ReRAM computing-in-memory macro with 11.91 to 195.7 TOPS/W for tiny AI edge devices CX Xue, JM Hung, HY Kao, YH Huang, SP Huang, FC Chang, P Chen, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 245-247, 2021 | 169 | 2021 |
| 19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme MF Chang, JJ Wu, TF Chien, YC Liu, TC Yang, WC Shen, YC King, CJ Lin, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 146 | 2014 |
| A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous … H Fujiwara, H Mori, WC Zhao, MC Chuang, R Naous, CK Chuang, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 137 | 2022 |
| A CMOS-integrated compute-in-memory macro based on resistive random-access memory for AI edge devices CX Xue, YC Chiu, TW Liu, TY Huang, JS Liu, TW Chang, HY Kao, ... Nature Electronics 4 (1), 81-90, 2021 | 125 | 2021 |
| An N40 256K× 44 embedded RRAM macro with SL-precharge SA and low-voltage current limiter to improve read and write performance CC Chou, ZJ Lin, PL Tseng, CF Li, CY Chang, WC Chen, YD Chih, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 478-480, 2018 | 122 | 2018 |
| An offset-tolerant fast-random-read current-sampling-based sense amplifier for small-cell-current nonvolatile memory MF Chang, SJ Shen, CC Liu, CW Wu, YF Lin, YC King, CJ Lin, HJ Liao, ... IEEE Journal of Solid-State Circuits 48 (3), 864-877, 2013 | 109 | 2013 |
| A 0.5 V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time MF Chang, CW Wu, CC Kuo, SJ Shen, KF Lin, SM Yang, YC King, CJ Lin, ... 2012 IEEE International Solid-State Circuits Conference, 434-436, 2012 | 93 | 2012 |
| A 1Mb 28nm STT-MRAM with 2.8 ns read access time at 1.2 V VDD using single-cap offset-cancelled sense amplifier and in-situ self-write-termination Q Dong, Z Wang, J Lim, Y Zhang, YC Shih, YD Chih, J Chang, D Blaauw, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 480-482, 2018 | 90 | 2018 |
| 29.1 A 40nm 64Kb 56.67 TOPS/W read-disturb-tolerant compute-in-memory/digital RRAM macro with active-feedback-based read and in-situ write verification JH Yoon, M Chang, WS Khwa, YD Chih, MF Chang, A Raychowdhury 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 404-406, 2021 | 86 | 2021 |
| 13.3 a 22nm 32mb embedded stt-mram with 10ns read speed, 1m cycle write endurance, 10 years retention at 150 c and high immunity to magnetic field interference YD Chih, YC Shih, CF Lee, YA Chang, PH Lee, HJ Lin, YL Chen, CP Lo, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 222-224, 2020 | 86 | 2020 |
| An 8-Mb DC-current-free binary-to-8b precision ReRAM nonvolatile computing-in-memory macro using time-space-readout with 1286.4-21.6 TOPS/W for edge-AI devices JM Hung, YH Huang, SP Huang, FC Chang, TH Wen, CI Su, WS Khwa, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 83 | 2022 |
| High density and ultra small cell size of contact ReRAM (CR-RAM) in 90nm CMOS logic technology and circuits YH Tseng, CE Huang, CH Kuo, YD Chih, CJ Lin 2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009 | 77 | 2009 |
| A four-megabit compute-in-memory macro with eight-bit precision based on CMOS and resistive random-access memory for AI edge devices JM Hung, CX Xue, HY Kao, YH Huang, FC Chang, SP Huang, TW Liu, ... Nature Electronics 4 (12), 921-930, 2021 | 75 | 2021 |
| A 22nm 96KX144 RRAM macro with a self-tracking reference and a low ripple charge pump to achieve a configurable read window and a wide operating voltage range CC Chou, ZJ Lin, CA Lai, CI Su, PL Tseng, WC Chen, WC Tsai, WT Chu, ... 2020 IEEE Symposium on VLSI Circuits, 1-2, 2020 | 73 | 2020 |
| A 22nm 4Mb STT-MRAM data-encrypted near-memory computation macro with a 192GB/s read-and-decryption bandwidth and 25.1-55.1 TOPS/W 8b MAC for AI operations YC Chiu, CS Yang, SH Teng, HY Huang, FC Chang, Y Wu, YA Chien, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 178-180, 2022 | 61 | 2022 |
| A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and In Situ Self-Write-Termination Q Dong, Z Wang, J Lim, Y Zhang, ME Sinangil, YC Shih, YD Chih, ... IEEE Journal of Solid-State Circuits 54 (1), 231-239, 2018 | 59 | 2018 |
| CHIMERA: A 0.92 TOPS, 2.2 TOPS/W edge AI accelerator with 2 MByte on-chip foundry resistive RAM for efficient training and inference M Giordano, K Prabhu, K Koul, RM Radway, A Gural, R Doshi, ZF Khan, ... 2021 symposium on VLSI circuits, 1-2, 2021 | 57 | 2021 |
| SAPIENS: A 64-kb RRAM-based non-volatile associative memory for one-shot learning and inference at the edge H Li, WC Chen, A Levy, CH Wang, H Wang, PH Chen, W Wan, WS Khwa, ... IEEE Transactions on Electron Devices 68 (12), 6637-6643, 2021 | 56 | 2021 |
| A 40nm 64kb 26.56TOPS/W 2.37Mb/mm2RRAM Binary/Compute-in-Memory Macro with 4.23x Improvement in Density and >75% Use of Sensing Dynamic Range SD Spetalnick, M Chang, B Crafton, WS Khwa, YD Chih, MF Chang, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 54 | 2022 |
