| A 3-GHz 70-Mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply K Zhang, U Bhattacharya, Z Chen, F Hamzaoglu, D Murray, N Vallepalli, ... IEEE Journal of Solid-State Circuits 41 (1), 146-151, 2005 | 462 | 2005 |
| SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction K Zhang, U Bhattacharya, Z Chen, F Hamzaoglu, D Murray, N Vallepalli, ... IEEE Journal of Solid-State Circuits 40 (4), 895-901, 2005 | 305 | 2005 |
| A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry E Karl, Y Wang, YG Ng, Z Guo, F Hamzaoglu, U Bhattacharya, K Zhang, ... 2012 IEEE International Solid-State Circuits Conference, 230-232, 2012 | 232 | 2012 |
| Circuit-level techniques to control gate leakage for sub-100nm CMOS F Hamzaoglu, MR Stan Proceedings of the 2002 international symposium on Low power electronics and …, 2002 | 190 | 2002 |
| MRAM as embedded non-volatile memory solution for 22FFL FinFET technology O Golonzka, JG Alzate, U Arslan, M Bohr, P Bai, J Brockman, B Buford, ... 2018 IEEE International Electron Devices Meeting (IEDM), 18.1. 1-18.1. 4, 2018 | 155 | 2018 |
| 13.2 A 3.6Mb 10.1Mb/mm2 Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology with Adaptive Forming/Set/Reset Schemes Yielding Down to 0.5V … P Jain, U Arslan, M Sekhar, BC Lin, L Wei, T Sahu, J Alzate-Vinasco, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 212-214, 2019 | 149 | 2019 |
| 13.3 A 7Mb STT-MRAM in 22FFL FinFET technology with 4ns read sensing time at 0.9 V using write-verify-write scheme and offset-cancellation sensing technique L Wei, JG Alzate, U Arslan, J Brockman, N Das, K Fischer, T Ghani, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 214-216, 2019 | 139 | 2019 |
| A 1.1 GHz 12 A/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications Y Wang, HJ Ahn, U Bhattacharya, Z Chen, T Coan, F Hamzaoglu, ... IEEE Journal of Solid-State Circuits 43 (1), 172-179, 2008 | 138 | 2008 |
| Multi-phase 1 GHz voltage doubler charge pump in 32 nm logic process D Somasekhar, B Srinivasan, G Pandya, F Hamzaoglu, M Khellah, ... IEEE Journal of Solid-State Circuits 45 (4), 751-758, 2010 | 128 | 2010 |
| 16.2 eDRAM-CIM: Compute-in-memory design with reconfigurable embedded-dynamic-memory array realizing adaptive data converters and charge-domain computing S Xie, C Ni, A Sayal, P Jain, F Hamzaoglu, JP Kulkarni 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 248-250, 2021 | 109 | 2021 |
| 2 MB array-level demonstration of STT-MRAM process and performance towards L4 cache applications JG Alzate, U Arslan, P Bai, J Brockman, YJ Chen, N Das, K Fischer, ... 2019 IEEE International Electron Devices Meeting (IEDM), 2.4. 1-2.4. 4, 2019 | 107 | 2019 |
| Dual-VT SRAM cells with full-swing single-ended bit line sensing for high-performance on-chip cache in 0.13 μm technology generation F Hamzaoglu, Y Te, A Keshavarzi, K Zhang, S Narendra, S Borkar, M Stan, ... Proceedings of the 2000 international symposium on Low power electronics and …, 2000 | 105 | 2000 |
| SRAM design on 65nm CMOS technology with integrated leakage reduction scheme K Zhang, U Bhattacharya, Z Chen, F Hamzaoglu, D Murray, N Vallepalli, ... 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No …, 2004 | 104 | 2004 |
| A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management Y Wang, U Bhattacharya, F Hamzaoglu, P Kolar, Y Ng, L Wei, Y Zhang, ... 2009 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2009 | 79 | 2009 |
| A 4.6 GHz 162 Mb SRAM design in 22 nm tri-gate CMOS technology with integrated read and write assist circuitry E Karl, Y Wang, YG Ng, Z Guo, F Hamzaoglu, M Meterelliyoz, J Keane, ... IEEE Journal of Solid-State Circuits 48 (1), 150-158, 2012 | 76 | 2012 |
| A 256-Kb Dual- SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor M Khellah, D Somasekhar, Y Ye, NS Kim, J Howard, G Ruhl, M Sunna, ... IEEE Journal of Solid-State Circuits 42 (1), 233-242, 2006 | 75 | 2006 |
| Non-volatile RRAM embedded into 22FFL FinFET technology O Golonzka, U Arslan, P Bai, M Bohr, O Baykan, Y Chang, A Chaudhari, ... 2019 Symposium on VLSI Technology, T230-T231, 2019 | 72 | 2019 |
| 13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology F Hamzaoglu, U Arslan, N Bisnik, S Ghosh, MB Lal, N Lindert, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 69 | 2014 |
| A 153Mb-SRAM design with dynamic stability enhancement and leakage reduction in 45nm high-κ metal-gate CMOS technology F Hamzaoglu, K Zhang, Y Wang, HJ Ahn, U Bhattacharya, Z Chen, YG Ng, ... 2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008 | 69 | 2008 |
| A 3.8 GHz 153 Mb SRAM design with dynamic stability enhancement and leakage reduction in 45 nm high-k metal gate CMOS technology F Hamzaoglu, K Zhang, Y Wang, HJ Ahn, U Bhattacharya, Z Chen, YG Ng, ... IEEE Journal of Solid-State Circuits 44 (1), 148-154, 2008 | 65 | 2008 |