| Full gate voltage range Lambert-function based methodology for FDSOI MOSFET parameter extraction TA Karatsori, CG Theodorou, EG Ioannidis, S Haendler, E Josse, ... Solid-State Electronics 111, 123-128, 2015 | 61 | 2015 |
| Low-frequency noise sources in advanced UTBB FD-SOI MOSFETs CG Theodorou, EG Ioannidis, F Andrieu, T Poiroux, O Faynot, ... IEEE Transactions on Electron Devices 61 (4), 1161-1167, 2014 | 56 | 2014 |
| Performance and low-frequency noise of 22-nm FDSOI down to 4.2 K for cryogenic applications BC Paz, M Cassé, C Theodorou, G Ghibaudo, T Kammler, L Pirro, M Vinet, ... IEEE Transactions on Electron Devices 67 (11), 4563-4567, 2020 | 52 | 2020 |
| Comparison for 1/ Noise Characteristics of AlGaN/GaN FinFET and Planar MISHFET S Vodapally, CG Theodorou, Y Bae, G Ghibaudo, S Cristoloveanu, KS Im, ... IEEE Transactions on Electron Devices 64 (9), 3634-3638, 2017 | 43 | 2017 |
| Origin of low-frequency noise in the low drain current range of bottom-gate amorphous IGZO thin-film transistors CG Theodorou, A Tsormpatzoglou, CA Dimitriadis, SA Khan, MK Hatalis, ... IEEE electron device letters 32 (7), 898-900, 2011 | 43 | 2011 |
| Analytical modeling of threshold voltage and interface ideality factor of nanoscale ultrathin body and buried oxide SOI MOSFETs with back gate control N Fasarakis, T Karatsori, DH Tassis, CG Theodorou, F Andrieu, O Faynot, ... IEEE Transactions on Electron Devices 61 (4), 969-975, 2014 | 42 | 2014 |
| Impact of source–drain series resistance on drain current mismatch in advanced fully depleted SOI n-MOSFETs EG Ioannidis, CG Theodorou, S Haendler, E Josse, CA Dimitriadis, ... IEEE Electron Device Letters 36 (5), 433-435, 2015 | 41 | 2015 |
| Drain-current flicker noise modeling in nMOSFETs from a 14-nm FDSOI technology EG Ioannidis, CG Theodorou, TA Karatsori, S Haendler, CA Dimitriadis, ... IEEE Transactions on Electron Devices 62 (5), 1574-1579, 2015 | 34 | 2015 |
| All operation region characterization and modeling of drain and gate current mismatch in 14-nm fully depleted SOI MOSFETs TA Karatsori, CG Theodorou, E Josse, CA Dimitriadis, G Ghibaudo IEEE Transactions on Electron Devices 64 (5), 2080-2085, 2017 | 33 | 2017 |
| Origin of the low-frequency noise in n-channel FinFETs CG Theodorou, N Fasarakis, T Hoffman, T Chiarella, G Ghibaudo, ... Solid-state electronics 82, 21-24, 2013 | 29 | 2013 |
| Symmetrical unified compact model of short-channel double-gate MOSFETs K Papathanasiou, CG Theodorou, A Tsormpatzoglou, DH Tassis, ... Solid-state electronics 69, 55-61, 2012 | 29 | 2012 |
| Low-frequency noise characteristics of GaN nanowire gate-all-around transistors with/without 2-DEG channel KS Im, MSP Reddy, R Caulmilone, CG Theodorou, G Ghibaudo, ... IEEE Transactions on Electron Devices 66 (3), 1243-1248, 2019 | 25 | 2019 |
| Analytical compact model for lightly doped nanoscale ultrathin-body and box SOI MOSFETs with back-gate control TA Karatsori, A Tsormpatzoglou, CG Theodorou, EG Ioannidis, ... IEEE Transactions on Electron Devices 62 (10), 3117-3124, 2015 | 24 | 2015 |
| New LFN and RTN analysis methodology in 28 and 14nm FD-SOI MOSFETs CG Theodorou, EG Ioannidis, S Haendler, N Planes, E Josse, ... 2015 IEEE international reliability physics symposium, XT. 1.1-XT. 1.6, 2015 | 24 | 2015 |
| Impact of front-back gate coupling on low frequency noise in 28 nm FDSOI MOSFETs CG Theodorou, EG Ioannidis, S Haendler, N Planes, F Arnaud, J Jomaah, ... 2012 Proceedings of the European Solid-State Device Research Conference …, 2012 | 24 | 2012 |
| Effect of gate structure on the trapping behavior of GaN junctionless FinFETs KS Im, SJ An, CG Theodorou, G Ghibaudo, S Cristoloveanu, JH Lee IEEE Electron Device Letters 41 (6), 832-835, 2020 | 22 | 2020 |
| Low frequency noise variability in ultra scaled FD-SOI n-MOSFETs: Dependence on gate bias, frequency and temperature CG Theodorou, EG Ioannidis, S Haendler, E Josse, CA Dimitriadis, ... Solid-State Electronics 117, 88-93, 2016 | 22 | 2016 |
| Evolution of low frequency noise and noise variability through CMOS bulk technology nodes from 0.5 μm down to 20 nm EG Ioannidis, S Haendler, CG Theodorou, S Lasserre, CA Dimitriadis, ... Solid-State Electronics 95, 28-31, 2014 | 22 | 2014 |
| Lambert-W function-based parameter extraction for FDSOI MOSFETs down to deep cryogenic temperatures FS di Santa Maria, L Contamin, BC Paz, M Cassé, C Theodorou, ... Solid-State Electronics 186, 108175, 2021 | 20 | 2021 |
| Statistical analysis of dynamic variability in 28nm FD-SOI MOSFETs EG Ioannidis, S Haendler, CG Theodorou, N Planes, CA Dimitriadis, ... 2014 44th European Solid State Device Research Conference (ESSDERC), 214-217, 2014 | 17 | 2014 |
Gerard GhibaudoIMEP-LAHC, Minatec-INP GrenobleVerified email at minatec.inpg.fr