| Testing the interconnect of RAM-based FPGAs M Renovell, JM Portal, J Figueras, Y Zorian IEEE Design & Test of Computers 15 (1), 45-50, 1998 | 218 | 1998 |
| Robust compact model for bipolar oxide-based resistive switching memories M Bocquet, D Deleruyelle, H Aziza, C Muller, JM Portal, T Cabout, ... IEEE transactions on electron devices 61 (3), 674-681, 2014 | 145 | 2014 |
| Synchronous non-volatile logic gate design based on resistive switching memories W Zhao, M Moreau, E Deng, Y Zhang, JM Portal, JO Klein, M Bocquet, ... IEEE Transactions on Circuits and Systems I: Regular Papers 61 (2), 443-454, 2013 | 124 | 2013 |
| EEPROM memory: Threshold voltage built in self diagnosis JM Portal, H Aziza International Test Conference, 2003. Proceedings. ITC 2003., 23-23, 2003 | 103 | 2003 |
| In-Memory and Error-Immune Differential RRAM Implementation of Binarized Deep Neural Networks M Bocquet, T Hirztlin, JO Klein, E Nowak, E Vianello, JM Portal, ... 2018 IEEE International Electron Devices Meeting (IEDM), 20.6. 1-20.6. 4, 2018 | 95 | 2018 |
| Definition of an innovative filling structure for digital blocks: the DFM filler cell L Remy, P Coll, F Picot, P Mico, JM Portal 2009 16th IEEE International Conference on Electronics, Circuits and Systems …, 2009 | 89 | 2009 |
| EEPROM diagnosis based on threshold voltage embedded measurement JM Portal, H Aziza, D Née Journal of Electronic Testing 21, 33-42, 2005 | 88 | 2005 |
| Self-consistent physical modeling of set/reset operations in unipolar resistive-switching memories M Bocquet, D Deleruyelle, C Muller, JM Portal Applied Physics Letters 98 (26), 2011 | 75 | 2011 |
| Digital biologically plausible implementation of binarized neural networks with differential hafnium oxide resistive memory arrays T Hirtzlin, M Bocquet, B Penkovsky, JO Klein, E Nowak, E Vianello, ... Frontiers in neuroscience 13, 1383, 2020 | 74 | 2020 |
| SRAM-based FPGA's: testing the LUT/RAM modules M Renovell, JM Portal, J Figueras, Y Zorian Proceedings International Test Conference 1998 (IEEE Cat. No. 98CH36270 …, 1998 | 68 | 1998 |
| IS-FPGA: a new symmetric FPGA architecture with implicit scan M Renovell, P Faure, JM Portal, J Figueras, Y Zorian Proceedings International Test Conference 2001 (Cat. No. 01CH37260), 924-931, 2001 | 66 | 2001 |
| RRAM-based FPGA for" Normally off, Instantly on" Applications O Turkyilmaz, S Onkaraiah, M Reyboz, F Clermidy, Hraziia, C Anghel, ... Proceedings of the 2012 IEEE/ACM international symposium on nanoscale …, 2012 | 55 | 2012 |
| Outstanding bit error tolerance of resistive RAM-based binarized neural networks T Hirtzlin, M Bocquet, JO Klein, E Nowak, E Vianello, JM Portal, ... 2019 IEEE International Conference on Artificial Intelligence Circuits and …, 2019 | 50 | 2019 |
| High-density 3D monolithically integrated multiple 1T1R multi-level-cell for neural networks E Esmanhotto, L Brunet, N Castellani, D Bonnet, T Dalgaty, L Grenouillet, ... 2020 IEEE International Electron Devices Meeting (IEDM), 36.5. 1-36.5. 4, 2020 | 49 | 2020 |
| Compact modeling solutions for oxide-based resistive switching memories (OxRAM) M Bocquet, H Aziza, W Zhao, Y Zhang, S Onkaraiah, C Muller, M Reyboz, ... Journal of Low Power Electronics and Applications 4 (1), 1-14, 2014 | 49 | 2014 |
| Bipolar ReRAM based non-volatile flip-flops for low-power architectures S Onkaraiah, M Reyboz, F Clermidy, JM Portal, M Bocquet, C Muller, ... 10th IEEE International NEWCAS Conference, 417-420, 2012 | 48 | 2012 |
| Minimizing the number of test configurations for different FPGA families M Renovell, JM Portal, J Figuras, Y Zorian Proceedings Eighth Asian Test Symposium (ATS'99), 363-368, 1999 | 48 | 1999 |
| Stochastic computing for hardware implementation of binarized neural networks T Hirtzlin, B Penkovsky, M Bocquet, JO Klein, JM Portal, D Querlioz IEEE Access 7, 76394-76403, 2019 | 47 | 2019 |
| Test pattern and test configuration generation methodology for the logic of RAM-based FPGA M Renovell, JM Portal, J Figueras, Y Zorian Proceedings Sixth Asian Test Symposium (ATS'97), 254-259, 1997 | 44 | 1997 |
| RAM-based FPGAs: A test approach for the configurable logic M Renovell, JM Portal, J Figueras, Y Zorian Proceedings Design, Automation and Test in Europe, 82-88, 1998 | 42 | 1998 |
Marc BocquetUniversité Aix-Marseille, IM2NPVerified email at im2np.fr
