| Confined epitaxial lateral overgrowth (CELO): A novel concept for scalable integration of CMOS-compatible InGaAs-on-insulator MOSFETs on large-area Si substrates L Czornomaz, E Uccelli, M Sousa, V Deshpande, V Djara, D Caimi, ... 2015 Symposium on VLSI Technology (VLSI Technology), T172-T173, 2015 | 99 | 2015 |
| A tunable, dual mode field-effect or single electron transistor B Roche, B Voisin, X Jehl, R Wacquez, M Sanquer, M Vinet, ... Applied Physics Letters 100 (3), 2012 | 58 | 2012 |
| Roadmap on ferroelectric hafnia-and zirconia-based materials and devices JPB Silva, R Alcala, UE Avci, N Barrett, L Bégon-Lours, M Borg, S Byun, ... APL Materials 11 (8), 2023 | 52 | 2023 |
| Advanced 3D monolithic hybrid CMOS with sub-50 nm gate inverters featuring replacement metal gate (RMG)-InGaAs nFETs on SiGe-OI fin pFETs V Deshpande, V Djara, E O'Connor, P Hashemi, K Balakrishnan, M Sousa, ... 2015 IEEE International Electron Devices Meeting (IEDM), 8.8. 1-8.8. 4, 2015 | 49 | 2015 |
| CMOS-Compatible Replacement Metal Gate InGaAs-OI FinFET WithatV andnA/ V Djara, V Deshpande, M Sousa, D Caimi, L Czornomaz, J Fompeyrine IEEE Electron Device Letters 37 (2), 169-172, 2016 | 46 | 2016 |
| Self-aligned gates for scalable silicon quantum computing S Geyer, LC Camenzind, L Czornomaz, V Deshpande, A Fuhrer, ... Applied Physics Letters 118 (10), 2021 | 43 | 2021 |
| Ambipolar quantum dots in undoped silicon fin field-effect transistors AV Kuhlmann, V Deshpande, LC Camenzind, DM Zumbühl, A Fuhrer Applied Physics Letters 113 (12), 2018 | 39 | 2018 |
| First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers A Vandooren, J Franco, Z Wu, B Parvais, W Li, L Witters, A Walke, L Peng, ... 2018 IEEE International Electron Devices Meeting (IEDM), 7.1. 1-7.1. 4, 2018 | 37 | 2018 |
| An InGaAs on Si platform for CMOS with 200 mm InGaAs-OI substrate, gate-first, replacement gate planar and FinFETs down to 120 nm contact pitch V Djara, V Deshpande, E Uccelli, N Daix, D Caimi, C Rossel, M Sousa, ... 2015 Symposium on VLSI Technology (VLSI Technology), T176-T177, 2015 | 37 | 2015 |
| Scaling of trigate nanowire (NW) MOSFETs to sub-7 nm width: 300 K transition to single electron transistor V Deshpande, S Barraud, X Jehl, R Wacquez, M Vinet, R Coquand, ... Solid-state electronics 84, 179-184, 2013 | 32 | 2013 |
| Three-dimensional monolithic integration of III–V and Si (Ge) FETs for hybrid CMOS and beyond V Deshpande, V Djara, E O’Connor, P Hashemi, T Morf, K Balakrishnan, ... Japanese Journal of Applied Physics 56 (4S), 04CA05, 2017 | 28 | 2017 |
| Single dopant impact on electrical characteristics of SOI NMOSFETs with effective length down to 10nm R Wacquez, M Vinet, M Pierre, B Roche, X Jehl, O Cueto, J Verduijn, ... 2010 Symposium on VLSI Technology, 193-194, 2010 | 27 | 2010 |
| First demonstration of III-V HBTs on 300 mm Si substrates using nano-ridge engineering A Vais, L Witters, Y Mols, AS Hernandez, A Walke, H Yu, M Baryshnikova, ... 2019 IEEE International Electron Devices Meeting (IEDM), 9.1. 1-9.1. 4, 2019 | 26 | 2019 |
| First demonstration of InGaAs/SiGe CMOS inverters and dense SRAM arrays on Si using selective epitaxy and standard FEOL processes L Czornomaz, V Djara, V Deshpande, E O'Connor, M Sousa, D Caimi, ... 2016 IEEE Symposium on VLSI Technology, 1-2, 2016 | 24 | 2016 |
| A scaled replacement metal gate InGaAs-on-Insulator n-FinFET on Si with record performance H Hahn, V Deshpande, E Caruso, S Sant, E O'Connor, Y Baumgartner, ... 2017 IEEE International Electron Devices Meeting (IEDM), 17.5. 1-17.5. 4, 2017 | 23 | 2017 |
| Resistive memory device L Czornomaz, VV Deshpande, VSP Jonnalagadda, W Koelmans, ... US Patent 9,570,169, 2017 | 21 | 2017 |
| Optical synapse for neuromorphic networks S Abel, L Czomomaz, VV Deshpande, J Fompeyrine US Patent 10,657,440, 2020 | 20 | 2020 |
| 3-D sequential stacked planar devices featuring low-temperature replacement metal gate junctionless top devices with improved reliability A Vandooren, J Franco, B Parvais, Z Wu, L Witters, A Walke, W Li, L Peng, ... IEEE Transactions on Electron Devices 65 (11), 5165-5171, 2018 | 20 | 2018 |
| InGaAs-on-insulator MOSFETs featuring scaled logic devices and record RF performance CB Zota, C Convertino, V Deshpande, T Merkle, M Sousa, D Caimi, ... 2018 IEEE Symposium on VLSI Technology, 165-166, 2018 | 20 | 2018 |
| First demonstration of 3D SRAM through 3D monolithic integration of InGaAs n-FinFETs on FDSOI Si CMOS with inter-layer contacts V Deshpande, H Hahn, E O'Connor, Y Baumgartner, M Sousa, D Caimi, ... 2017 Symposium on VLSI Technology, T74-T75, 2017 | 20 | 2017 |
