| Deep learning neural network classifier using non-volatile memory array FM Bayat, X Guo, D Strukov, N Do, H Van Tran, V Tiwari, M Reiten US Patent 11,308,383, 2022 | 109 | 2022 |
| Embedded flash memory for security applications in a 0.13/spl mu/m CMOS logic process J Raszka, M Advani, V Tiwari, L Varisco, ND Hacobian, A Mittal, M Han, ... 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No …, 2004 | 102 | 2004 |
| High precision and highly efficient tuning mechanisms and algorithms for analog neuromorphic memory in artificial neural networks H Van Tran, V Tiwari, N Do, S Lemke, S Hariharan, S Hong US Patent 10,748,630, 2020 | 44 | 2020 |
| Flash memory array with individual memory cell read, program and erase X Guo, FM Bayat, D Strukov, N Do, H Van Tran, V Tiwari US Patent 10,269,440, 2019 | 30 | 2019 |
| Array of three-gate flash memory cells with individual memory cell read, program and erase H Van Tran, V Tiwari, N Do US Patent 10,311,958, 2019 | 26 | 2019 |
| System and method for implementing configurable convoluted neural networks with flash memories V Tiwari, N Do US Patent 10,580,492, 2020 | 22 | 2020 |
| Flash memory array with individual memory cell read, program and erase X Guo, FM Bayat, D Strukov, N Do, H Van Tran, V Tiwari US Patent 10,249,375, 2019 | 21 | 2019 |
| Memory cell sensing with low noise generation J Raszka, VK Tiwari US Patent 7,184,346, 2007 | 18 | 2007 |
| Neural network classifier using array of two-gate non-volatile memory cells H Van Tran, S Lemke, V Tiwari, N Do, M Reiten US Patent 10,699,779, 2020 | 17 | 2020 |
| A cost-efficient 28nm split-gate eFLASH memory featuring a HKMG hybrid bit cell and HV device R Richter, M Trentzsch, S Dünkel, J Müller, P Moll, B Bayha, K Mothes, ... 2018 IEEE International Electron Devices Meeting (IEDM), 18.5. 1-18.5. 4, 2018 | 14 | 2018 |
| Memory cell sensing with low noise generation J Raszka, VK Tiwari US Patent 6,850,446, 2005 | 13 | 2005 |
| Ultra-precise tuning of analog neural memory cells in a deep learning artificial neural network S Lemke, H Van Tran, Y Tkachev, L Schneider, HA Om'Mani, T Vu, N Do, ... US Patent 11,393,535, 2022 | 12 | 2022 |
| Split-Gate Floating Poly SuperFlash® Memory Technology, Design, and Reliability N Do, H Van Tran, A Kotov, V Tiwari Embedded Flash memory for embedded systems: technology, design for sub …, 2018 | 12 | 2018 |
| 40nm embedded self-aligned split-gate flash technology for high-density automotive microcontrollers D Shum, LQ Luo, YJ Kong, FX Deng, X Qu, ZQ Teo, JQ Liu, F Zhang, ... 2017 IEEE International Memory Workshop (IMW), 1-4, 2017 | 11 | 2017 |
| Method and apparatus for high voltage generation for analog neural memory in deep learning artificial neural network H Van Tran, T Vu, S Hong, A Ly, V Tiwari, N Do US Patent 10,522,226, 2019 | 10 | 2019 |
| High density split-gate memory cell N Do, X Liu, V Tiwari, H Van Tran US Patent 10,658,027, 2020 | 9 | 2020 |
| Power Driven Optimization For Flash Memory V Tiwari, N Do US Patent App. 15/244,947, 2017 | 9 | 2017 |
| Method and apparatus for programming analog neural memory in a deep learning artificial neural network H Van Tran, V Tiwari, N Do, M Reiten US Patent 10,910,061, 2021 | 8 | 2021 |
| Scaling of split-gate flash memory with 1.05 V select transistor for 28 nm embedded flash technology N Do, JW Yang, YJ Sheng, CS Su, MT Wu, H Ouyang, H Liang, ... 2018 IEEE International Memory Workshop (IMW), 1-3, 2018 | 8 | 2018 |
| Configurable input blocks and output blocks and physical layout for analog neural memory in deep learning artificial neural network H Van Tran, S Trinh, T Vu, S Hong, V Tiwari, M Reiten, N Do US Patent 11,507,642, 2022 | 7 | 2022 |
