| 8 Gb 3-D DDR3 DRAM using through-silicon-via technology U Kang, HJ Chung, S Heo, DH Park, H Lee, JH Kim, SH Ahn, SH Cha, ... IEEE Journal of Solid-State Circuits 45 (1), 111-119, 2009 | 686 | 2009 |
| A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems J Kennedy, R Mooney, R Ellis, J Jaussi, S Borkar, JH Choi, JK Kim, ... IEEE journal of solid-state circuits 40 (1), 233-244, 2005 | 107 | 2005 |
| A 1.2 V 20 nm 307 GB/s HBM DRAM with at-speed wafer-level IO test scheme and adaptive refresh considering temperature distribution K Sohn, WJ Yun, R Oh, CS Oh, SY Seo, MS Park, DH Shin, WC Jung, ... IEEE Journal of Solid-State Circuits 52 (1), 250-260, 2016 | 105 | 2016 |
| A 3.6 Gb/s/pin simultaneous bidirectional (SBD) I/O interface for high-speed DRAM JK Kim, JH Choi, SW Shin, CK Kim, HY Kim, WS Kim, C Kim, SI Cho 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No …, 2004 | 92 | 2004 |
| A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme K Sohn, T Na, I Song, Y Shim, W Bae, S Kang, D Lee, H Jung, S Hyun, ... IEEE journal of solid-state circuits 48 (1), 168-177, 2012 | 80 | 2012 |
| A 16-Gb, 18-Gb/s/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking YJ Kim, HJ Kwon, SY Doo, M Ahn, YH Kim, YJ Lee, DS Kang, SG Do, ... IEEE Journal of Solid-State Circuits 54 (1), 197-209, 2018 | 59 | 2018 |
| Semiconductor device having additive latency YK Kim, JH Choi US Patent 8,358,546, 2013 | 49 | 2013 |
| Memory system JK Kim, JH Choi, SH Hyun US Patent App. 13/804,044, 2013 | 47 | 2013 |
| A 20GB/s 256Mb DRAM with an Inductorless Quadrature PLL and a Cascaded Pre-emphasis Transmitter KH Kim, YS Sohn, CK Kim, DJ Lee, GS Byun, H Lee, JH Lee, S Jung, ... 2005 IEEE International Solid-State Circuits Conference, 2005 | 41 | 2005 |
| A 1Tb 4b/cell NAND Flash Memory with t PROG= 2ms, t R= 110µs and 1.2 Gb/s High-Speed IO Rate DH Kim, H Kim, S Yun, Y Song, J Kim, SM Joe, KH Kang, J Jang, HJ Yoon, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 218-220, 2020 | 40 | 2020 |
| Stacked die package, system including the same, and method of manufacturing the same JK Kim, JH Choi US Patent 9,123,630, 2015 | 39 | 2015 |
| 1.2V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture Y Moon, YH Cho, HB Lee, BH Jeong, SH Hyun, BC Kim, IC Jeong, ... 2009 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2009 | 39 | 2009 |
| MEMORY DEVICE ADJUSTING DUTY CYCLE AND MEMORY SYSTEM HAVING THE SAME DS Moon, GH Cha, KS Oh, CK Lee, YK Choi, JH Choi, KS Ha, SH Hyun US Patent 10,923,175, 2021 | 37 | 2021 |
| Multi channel semiconductor device having multi dies and operation method thereof YJ Eom, JY Park, Y Bae, WY Lee, SJ Jang, JH Choi, J Choi US Patent 10,255,969, 2019 | 35 | 2019 |
| Systems and methods for correcting duty cycle deviations in clock and data signals JH Choi US Patent 6,181,178, 2001 | 35 | 2001 |
| A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme CK Lee, YJ Eom, JH Park, J Lee, HR Kim, K Kim, Y Choi, HJ Chang, J Kim, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 390-391, 2017 | 34 | 2017 |
| Bulk-Si photonics technology for DRAM interface H Byun, J Bok, K Cho, K Cho, H Choi, J Choi, S Choi, S Han, S Hong, ... Photonics Research 2 (3), A25-A33, 2014 | 33 | 2014 |
| A 4-Gb/s/pin low-power memory I/O interface using 4-level simultaneous bi-directional signaling JH Kim, S Kim, WS Kim, JH Choi, HS Hwang, C Kim, S Kim IEEE journal of solid-state circuits 40 (1), 89-101, 2005 | 31 | 2005 |
| Semiconductor device, controller associated therewith, system including the same, and methods of operation JH Choi US Patent 8,832,391, 2014 | 30 | 2014 |
| Receiving apparatus and method thereof YS Sohn, SJ Bae, HJ Park, JH Choi US Patent 7,822,111, 2010 | 28 | 2010 |
Chang-Kyo LeeAMDVerified email at kaist.ac.kr