| A g/sub m//i/sub d/based methodology for the design of cmos analog circuits and its application to the synthesis of a silicon-on-insulator micropower ota F Silveira, D Flandre, PGA Jespers IEEE journal of solid-state circuits 31 (9), 1314-1319, 1996 | 922 | 1996 |
| Substrate crosstalk reduction using SOI technology JP Raskin, A Viviani, D Flandre, JP Colinge IEEE Transactions on electron devices 44 (12), 2252-2261, 1997 | 413 | 1997 |
| Influence of device engineering on the analog and RF performances of SOI MOSFETs V Kilchytska, A Neve, L Vancaillie, D Levacq, S Adriaensen, H van Meer, ... IEEE Transactions on Electron Devices 50 (3), 577-588, 2003 | 272 | 2003 |
| A formal study of power variability issues and side-channel attacks for nanoscale devices M Renauld, FX Standaert, N Veyrat-Charvillon, D Kamel, D Flandre Advances in Cryptology–EUROCRYPT 2011: 30th Annual International Conference …, 2011 | 249 | 2011 |
| Modeling of ultrathin double-gate nMOS/SOI transistors P Francis, A Terao, D Flandre, F Van de Wiele IEEE Transactions on Electron Devices 41 (5), 715-720, 1994 | 216 | 1994 |
| Interests and limitations of technology scaling for subthreshold logic D Bol, R Ambroise, D Flandre, JD Legat IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17 (10 …, 2009 | 215 | 2009 |
| A capacitorless 1T-DRAM on SOI based on dynamic coupling and double-gate operation M Bawedin, S Cristoloveanu, D Flandre IEEE Electron Device Letters 29 (7), 795-798, 2008 | 215 | 2008 |
| ULPFA: A new efficient design of a power-aware full adder I Hassoune, D Flandre, I O'Connor, JD Legat IEEE Transactions on Circuits and Systems I: Regular Papers 57 (8), 2066-2074, 2008 | 186 | 2008 |
| SleepWalker: A 25-MHz 0.4-V Sub- 7- Microcontroller in 65-nm LP/GP CMOS for Low-Carbon Wireless Sensor Nodes D Bol, J De Vos, C Hocquet, F Botman, F Durvaux, S Boyd, D Flandre, ... IEEE Journal of Solid-State Circuits 48 (1), 20-32, 2012 | 185 | 2012 |
| Employing Si solar cell technology to increase efficiency of ultra‐thin Cu(In,Ga)Se2 solar cells B Vermang, JT Wätjen, V Fjällström, F Rostvall, M Edoff, R Kotipalli, ... Progress in Photovoltaics: Research and Applications 22 (10), 1023-1029, 2014 | 183 | 2014 |
| Design of SOI CMOS operational amplifiers for applications up to 300/spl deg/c JP Eggermont, D De Ceuster, D Flandre, B Gentinne, PGA Jespers, ... IEEE Journal of Solid-State Circuits 31 (2), 179-186, 1996 | 151 | 1996 |
| Micromachined thin-film sensors for SOI-CMOS co-integration J Laconte, D Flandre, JP Raskin Springer Science & Business Media, 2006 | 148 | 2006 |
| Analog/RF performance of multiple gate SOI devices: wideband simulations and characterization JP Raskin, TM Chung, V Kilchytska, D Lederer, D Flandre IEEE Transactions on Electron Devices 53 (5), 1088-1095, 2006 | 147 | 2006 |
| Comparison of TiSi2, CoSi2, and NiSi for thin‐film silicon‐on‐insulator applications J Chen, JP Colinge, D Flandre, R Gillon, JP Raskin, D Vanhoenacker Journal of the Electrochemical Society 144 (7), 2437, 1997 | 141 | 1997 |
| Analog performance and application of graded-channel fully depleted SOI MOSFETs MA Pavanello, JA Martino, V Dessard, D Flandre Solid-State Electronics 44 (7), 1219-1222, 2000 | 131 | 2000 |
| FinFET analogue characterization from DC to 110 GHz D Lederer, V Kilchytska, T Rudenko, N Collaert, D Flandre, A Dixit, ... Solid-State Electronics 49 (9), 1488-1496, 2005 | 127 | 2005 |
| Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications A Kranti, TM Chung, D Flandre, JP Raskin Solid-State Electronics 48 (6), 947-959, 2004 | 124 | 2004 |
| Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology D Flandre, A Viviani, JP Eggermont, B Gentinne, PGA Jespers IEEE journal of solid-state circuits 32 (7), 1006-1012, 1997 | 124 | 1997 |
| Measurement of threshold voltages of thin-film accumulation-mode PMOS/SOI transistors A Terao, D Flandre, E Lora-Tamayo, F Van de Wiele IEEE electron device letters 12 (12), 682-684, 1991 | 116 | 1991 |
| Fully depleted SOI CMOS technology for heterogeneous micropower, high-temperature or RF microsystems D Flandre, S Adriaensen, A Akheyar, A Crahay, L Demeûs, P Delatte, ... Solid-State Electronics 45 (4), 541-549, 2001 | 115 | 2001 |
