| A 7.6 mW, 414 fs RMS-jitter 10 GHz phase-locked loop for a 40 Gb/s serial link transmitter based on a two-stage ring oscillator in 65 nm CMOS W Bae, H Ju, K Park, SY Cho, DK Jeong IEEE Journal of Solid-State Circuits 51 (10), 2357-2367, 2016 | 80 | 2016 |
| 29.7 A 2.5GHz injection-locked ADPLL with 197fsrmsintegrated jitter and −65dBc reference spur using time-division dual calibration S Kim, HG Ko, SY Cho, J Lee, S Shin, MS Choo, H Chi, DK Jeong 2017 IEEE International Solid-State Circuits Conference (ISSCC), 494-495, 2017 | 37 | 2017 |
| A 4–20-Gb/s 1.87-pJ/b continuous-rate digital CDR circuit with unlimited frequency acquisition capability in 65-nm CMOS K Park, K Lee, SY Cho, J Lee, J Hwang, MS Choo, DK Jeong IEEE Journal of Solid-State Circuits 56 (5), 1597-1607, 2020 | 32 | 2020 |
| A 0.36 pJ/bit, 0.025 mm, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology W Bae, GS Jeong, K Park, SY Cho, Y Kim, DK Jeong IEEE Transactions on Circuits and Systems I: Regular Papers 63 (9), 1393-1403, 2016 | 31 | 2016 |
| A 2.5–5.6 GHz subharmonically injection-locked all-digital PLL with dual-edge complementary switched injection SY Cho, S Kim, MS Choo, HG Ko, J Lee, W Bae, DK Jeong IEEE Transactions on Circuits and Systems I: Regular Papers 65 (9), 2691-2702, 2018 | 29 | 2018 |
| A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection SY Cho, S Kim, MS Choo, J Lee, HG Ko, S Jang, SH Chu, W Bae, Y Kim, ... ESSCIRC Conference 2015-41st European Solid-State Circuits Conference …, 2015 | 26 | 2015 |
| A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant-Bias GS Jeong, SH Chu, Y Kim, S Jang, S Kim, W Bae, SY Cho, H Ju, ... IEEE Journal of Solid-State Circuits 51 (10), 2312-2327, 2016 | 25 | 2016 |
| A fast droop-recovery event-driven digital LDO with adaptive linear/binary two-step search for voltage regulation in advanced memory Y Song, J Oh, SY Cho, DK Jeong, JE Park IEEE Transactions on Power Electronics 37 (2), 1189-1194, 2021 | 21 | 2021 |
| An optimum injection-timing tracking loop for 5-GHz, 1.13-mW/GHz RO-based injection-locked PLL with 152-fs integrated jitter MS Choo, HG Ko, SY Cho, K Lee, DK Jeong IEEE Transactions on Circuits and Systems II: Express Briefs 65 (12), 1819-1823, 2018 | 15 | 2018 |
| A 15-GHz, 17.8-mW, 213-fs injection-locked PLL with maximized injection strength using adjustment of phase domain response MS Choo, Y Song, SY Cho, HG Ko, K Park, DK Jeong IEEE Transactions on Circuits and Systems II: Express Briefs 66 (12), 1932-1936, 2019 | 10 | 2019 |
| A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line W Bae, GS Jeong, K Park, SY Cho, Y Kim, DK Jeong ESSCIRC 2014-40th European Solid State Circuits Conference (ESSCIRC), 447-450, 2014 | 10 | 2014 |
| A 4-to-20Gb/s 1.87 pJ/b referenceless digital CDR with unlimited frequency detection capability in 65nm CMOS K Park, K Lee, SY Cho, J Lee, J Hwang, MS Choo, DK Jeong 2019 Symposium on VLSI Circuits, C194-C195, 2019 | 9 | 2019 |
| A PVT variation-robust all-digital injection-locked clock multiplier with real-time offset tracking using time-division dual calibration MS Choo, S Kim, HG Ko, SY Cho, K Park, J Lee, S Shin, H Chi, DK Jeong IEEE Journal of Solid-State Circuits 56 (8), 2525-2538, 2021 | 6 | 2021 |
| Injection-locked oscillator and semiconductor device including the same KIM Sungwoo, S Cho, CHI Hankyu, S Kim, DK Jeong US Patent 10,284,211, 2019 | 6 | 2019 |
| A 2.5–28 Gb/s multi-standard transmitter with two-step time-multiplexing driver MC Choi, SY Cho, M Shim, B Kim, HG Ko, H Ju, K Park, H Kim, K Kim, ... IEEE Transactions on Circuits and Systems II: Express Briefs 66 (12), 1927-1931, 2019 | 5 | 2019 |
| A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology MS Choo, K Park, HG Ko, SY Cho, K Lee, DK Jeong IEEE Journal of Solid-State Circuits 54 (10), 2812-2822, 2019 | 5 | 2019 |
| 13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration SY Cho, MC Choi, J Baek, D An, S Kim, D Lee, S Yang, GY Kang, J Park, ... 2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 242-244, 2024 | 4 | 2024 |
| A 285-fsrms Integrated Jitter Injection-Locked Ring PLL with Charge-Stored Complementary Switch Injection Technique S Kim, S Jang, SY Cho, MS Choo, GS Jeong, W Bae, DK Jeong Journal of semiconductor technology and science 16 (6), 860-866, 2016 | 4 | 2016 |
| A 1.93-pj/bit pci express gen4 phy transmitter with on-chip supply regulators in 28 nm cmos W Bae, SY Cho, DK Jeong Electronics 10 (1), 68, 2021 | 3 | 2021 |
| A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate All-Digital Injection-Locked Clock and Data Recovery with Maximum Timing-Margin Tracking Loop MS Choo, HG Ko, SY Cho, K Lee, DK Jeong 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), 73-76, 2018 | 3 | 2018 |