| ITRS 2.0: Toward a re-framing of the Semiconductor Technology Roadmap JA Carballo, WTJ Chan, PA Gargini, AB Kahng, S Nath 2014 IEEE 32nd international conference on computer design (ICCD), 139-146, 2014 | 130 | 2014 |
| Layout methodology impact of resolution enhancement techniques L Liebmann, JA Carballo Apr 6, 5-6, 2003 | 71 | 2003 |
| Method and system for providing constraint-based guidance to a designer in a collaborative design environment JA Carballo, SW Director US Patent 7,047,168, 2006 | 47 | 2006 |
| Level shifting, scannable latch, and method therefor JA Carballo US Patent 6,545,519, 2003 | 34 | 2003 |
| Method and system for interactive modeling of high-level network performance with low-level link design JA Carballo, K Nowka US Patent App. 10/829,829, 2005 | 25 | 2005 |
| Global management of local link power consumption JA Carballo US Patent 7,466,996, 2008 | 23 | 2008 |
| Digital transmission circuit and method providing selectable power consumption via multiple weighted drive slices JA Carballo, KJ Nowka, I Vo, SM Yoo US Patent 7,353,007, 2008 | 23 | 2008 |
| Method and apparatus for control of voltage regulation JA Carballo, KJ Nowka, I Vo US Patent 6,801,025, 2004 | 22 | 2004 |
| Digital transmission circuit and method providing selectable power consumption via single-ended or differential operation JA Carballo, KJ Nowka, I Vo, SM Yoo US Patent 7,522,670, 2009 | 20 | 2009 |
| One-sample-per-bit decision feedback equalizer (DFE) clock and data recovery JA Carballo, HC Cranford Jr, GJ Nicholls, VR Norman, ML Schmatz US Patent 7,809,054, 2010 | 17 | 2010 |
| Interleaved feedforward VCO and PLL DW Boerstler, JA Carballo, GD Carpenter, HC Ngo, KJ Nowka US Patent 6,529,084, 2003 | 17 | 2003 |
| Interface transceiver power management method and apparatus including controlled circuit complexity and power supply voltage JA Carballo, JL Burns US Patent 8,271,055, 2012 | 15 | 2012 |
| Method and apparatus for measuring communications link quality JA Carballo, JL Burns, I Vo US Patent 7,133,654, 2006 | 15 | 2006 |
| Interface transceiver power mangagement method and apparatus JA Carballo, D Boerstler, J Burns US Patent App. 10/289,777, 2004 | 14 | 2004 |
| A semi-custom voltage-island technique and its application to high-speed serial links JA Carballo, JL Burns, SM Yoo, I Vo, VR Norman Proceedings of the 2003 international symposium on Low power electronics and …, 2003 | 14 | 2003 |
| Impact of design-manufacturing interface on SoC design methodologies JA Carballo, SR Nassif IEEE Design & Test of Computers 21 (3), 183-191, 2004 | 13 | 2004 |
| Differential voltage controlled oscillator, and method therefor JA Carballo, DW Boerstler, JL Burns, I Vo US Patent 6,621,358, 2003 | 13 | 2003 |
| Constraint management for collaborative electronic design JA Carballo, SW Director Proceedings of the 36th annual ACM/IEEE Design Automation Conference, 529-534, 1999 | 13 | 1999 |
| Channel-based testing of communication link JA Carballo US Patent App. 10/687,257, 2005 | 11 | 2005 |
| Fast, symmetrical XOR/XNOR gate DW Boerstler, JA Carballo, RK Montoye US Patent 6,573,758, 2003 | 11 | 2003 |