| Design and evaluation of multiple valued logic gates using pseudo N-type carbon nanotube FETs J Liang, L Chen, J Han, F Lombardi IEEE transactions on nanotechnology 13 (4), 695-708, 2014 | 161 | 2014 |
| On the design of approximate restoring dividers for error-tolerant applications L Chen, J Han, W Liu, F Lombardi IEEE Transactions on Computers 65 (8), 2522-2533, 2015 | 81 | 2015 |
| Design of approximate unsigned integer non-restoring divider for inexact computing L Chen, J Han, W Liu, F Lombardi Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 51-56, 2015 | 78 | 2015 |
| Design and analysis of inexact floating-point adders W Liu, L Chen, C Wang, M O’Neill, F Lombardi IEEE Transactions on Computers 65 (1), 308-314, 2015 | 69 | 2015 |
| Algorithm and design of a fully parallel approximate coordinate rotation digital computer (CORDIC) L Chen, J Han, W Liu, F Lombardi IEEE Transactions on Multi-Scale Computing Systems 3 (3), 139-151, 2017 | 46 | 2017 |
| Design, evaluation and application of approximate high-radix dividers L Chen, J Han, W Liu, P Montuschi, F Lombardi IEEE Transactions on Multi-Scale Computing Systems 4 (3), 299-312, 2018 | 44 | 2018 |
| Efficient implementations of reduced precision redundancy (RPR) multiply and accumulate (MAC) K Chen, L Chen, P Reviriego, F Lombardi IEEE Transactions on Computers 68 (5), 784-790, 2018 | 35 | 2018 |
| Inexact floating-point adder for dynamic image processing W Liu, L Chen, C Wang, M O'Neill, F Lombardi 14th IEEE International Conference on Nanotechnology, 239-243, 2014 | 29 | 2014 |
| Design of approximate high-radix dividers by inexact binary signed-digit addition L Chen, F Lombardi, P Montuschi, J Han, W Liu Proceedings of the Great Lakes Symposium on VLSI 2017, 293-298, 2017 | 28 | 2017 |
| Design and reliability analysis of multiple valued logic gates using carbon nanotube FETs J Liang, J Han, L Chen, F Lombardi Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale …, 2012 | 15 | 2012 |
| A fully parallel approximate CORDIC design L Chen, F Lombardi, J Han, W Liu 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH …, 2016 | 9 | 2016 |
| FDSOI SRAM cells for low power design at 22nm technology node L Chen, F Lombardi, J Han 2014 IEEE 57th International Midwest Symposium on Circuits and Systems …, 2014 | 8 | 2014 |
| An enhanced HSPICE macromodel of a PCM cell with threshold switching and recovery behavior L Chen, F Lombardi, J Han 2014 IEEE 57th International Midwest Symposium on Circuits and Systems …, 2014 | 2 | 2014 |
| Low power designs using approximate computing and emerging memory at nanoscales L Chen Northeastern University, 2021 | 1 | 2021 |
| CCE: A Combined SRAM and Non Volatile Cache for Endurance of Next Generation Multilevel Non Volatile Memories in Embedded Systems L Chen, P Junsangsri, P Reviriego, F Lombardi Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale …, 2018 | 1 | 2018 |
| Design and operational assessment of an intra-cell hybrid L2 cache L Chen, J Han, W Liu, F Lombardi 2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 1-6, 2017 | 1 | 2017 |