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An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V} _ {\text {MIN}} $ Optimization
PA Meinerzhagen, C Tokunaga, A Malavasi, V Vaidya, A Mendon, ...
IEEE Journal of Solid-State Circuits 54 (1), 144-157, 2018
Mandates: US Department of Defense
Available somewhere: 4
Analysis of neutron-induced multibit-upset clusters in a 14-nm flip-flop array
S Kumar, M Cho, L Everson, Q Tang, P Meinerzhagen, A Malavasi, ...
IEEE Transactions on Nuclear Science 66 (6), 918-925, 2019
Mandates: US Department of Defense
Statistical characterization of radiation-induced pulse waveforms and flip-flop soft errors in 14nm tri-gate CMOS using a back-sampling chain (BSC) technique
S Kumar, M Cho, L Eversen, H Kim, Q Tang, P Mazanec, P Meinerzhagen, ...
2017 Symposium on VLSI Circuits, C114-C115, 2017
Mandates: US Department of Energy
An ultra-dense irradiation test structure with a NAND/NOR readout chain for characterizing soft error rates of 14nm combinational logic circuits
S Kumar, M Cho, L Everson, H Kim, Q Tang, P Mazanec, P Meinerzhagen, ...
2017 IEEE International Electron Devices Meeting (IEDM), 39.3. 1-39.3. 4, 2017
Mandates: US Department of Defense
A back-sampling chain technique for accelerated detection, characterization, and reconstruction of radiation-induced transient pulses
S Kumar, M Cho, LR Everson, A Malavasi, D Lake, C Tokunaga, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (12 …, 2021
Mandates: US Department of Defense
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