| Device and circuit co-design robustness studies in the subthreshold logic for ultralow-power applications for 32 nm CMOS R Vaddi, S Dasgupta, RP Agarwal IEEE Transactions on Electron Devices 57 (3), 654-664, 2010 | 194* | 2010 |
| Nanoscale FinFET based SRAM cell design: Analysis of performance metric, process variation, underlapped FinFET, and temperature effect B Raj, AK Saxena, S Dasgupta IEEE Circuits and Systems Magazine 11 (3), 38-50, 2011 | 149 | 2011 |
| Effect of well and substrate potential modulation on single event pulse shape in deep submicron CMOS S DasGupta, AF Witulski, BL Bhuva, ML Alles, RA Reed, OA Amusan, ... IEEE Transactions on Nuclear Science 54 (6), 2407-2412, 2007 | 133 | 2007 |
| Antifungal Activity of Some Plant Extracts Against Fungal Pathogens of Tea (Camellia sinensis.) D Saha, S Dasgupta, A Saha Pharmaceutical biology 43 (1), 87-91, 2005 | 101 | 2005 |
| A Comparative Study of 6T, 8T and 9T Decanano SRAM cell P Athe, S Dasgupta 2009 IEEE Symposium on Industrial Electronics & Applications 2, 889-894, 2009 | 98 | 2009 |
| Surface potential and drain current analytical model of gate all around triple metal TFET N Bagga, S Dasgupta IEEE Transactions on Electron Devices 64 (2), 606-613, 2017 | 85 | 2017 |
| Investigation of symmetric dual-k spacer trigate FinFETs from delay perspective PK Pal, BK Kaushik, S Dasgupta IEEE Transactions on Electron Devices 61 (11), 3579-3585, 2014 | 84 | 2014 |
| High-performance and robust SRAM cell based on asymmetric dual-k spacer FinFETs PK Pal, BK Kaushik, S Dasgupta IEEE Transactions on Electron Devices 60 (10), 3371-3377, 2013 | 81 | 2013 |
| Analytical modeling for the estimation of leakage current and subthreshold swing factor of nanoscale double gate FinFET device B Raj, AK Saxena, S Dasgupta Microelectronics International 26 (1), 53-63, 2009 | 77 | 2009 |
| Demonstration of a novel two source region tunnel FET N Bagga, A Kumar, S Dasgupta IEEE Transactions on Electron Devices 64 (12), 5256-5262, 2017 | 76 | 2017 |
| Design and analysis of analog performance of dual-k spacer underlap N/P-FinFET at 12 nm gate length A Nandi, AK Saxena, S Dasgupta IEEE transactions on electron devices 60 (5), 1529-1535, 2013 | 75 | 2013 |
| Recent trend of FinFET devices and its challenges: A review RS Pal, S Sharma, S Dasgupta 2017 Conference on Emerging Devices and Smart Systems (ICEDSS), 150-154, 2017 | 74 | 2017 |
| Analytical modeling of a double gate MOSFET considering source/drain lateral Gaussian doping profile A Nandi, AK Saxena, S Dasgupta IEEE Transactions on Electron Devices 60 (11), 3705-3709, 2013 | 65 | 2013 |
| Asymmetric dual-spacer trigate FinFET device-circuit codesign and its variability analysis PK Pal, BK Kaushik, S Dasgupta IEEE Transactions on Electron Devices 62 (4), 1105-1112, 2015 | 61 | 2015 |
| FPGA: An efficient and promising platform for real-time image processing applications S Mittal, S Gupta, S Dasgupta National Conference On Research and Development In Hardware Systems (CSI-RDHS), 2008 | 58 | 2008 |
| A compact drain current and threshold voltage quantum mechanical analytical modeling for FinFETs B Raj, AK Saxena, S Dasgupta Journal of Nanoelectronics and Optoelectronics (JNO), USA 3 (2), 163-170, 2008 | 56 | 2008 |
| Two dimensional analytical modeling for asymmetric 3T and 4T double gate tunnel FET in sub-threshold region: Potential and electric field M Yadav, A Bulusu, S Dasgupta Microelectronics Journal 44 (12), 1251-1259, 2013 | 54 | 2013 |
| Quantum mechanical analytical modeling of nanoscale DG FinFET: evaluation of potential, threshold voltage and source/drain resistance B Raj, AK Saxena, S Dasgupta Materials science in semiconductor processing 16 (4), 1131-1137, 2013 | 51 | 2013 |
| System generator: The state-of-art FPGA design tool for dsp applications S Mittal, S Gupta, S Dasgupta Third International Innovative Conference On Embedded Systems, Mobile …, 2008 | 44 | 2008 |
| Impact of random spatial fluctuation in non-uniform crystalline phases on the device variation of ferroelectric FET C Garg, N Chauhan, S Deng, AI Khan, S Dasgupta, A Bulusu, K Ni IEEE Electron Device Letters 42 (8), 1160-1163, 2021 | 39 | 2021 |
Bulusu AnandIndian Institute of Technology RoorkeeVerified email at ece.iitr.ac.in